SMD1108 Datasheet, PDF (14/29 Pages) Summit Microelectronics, Inc. – 8-Channel Auto-Monitor ADC In System Programmable Analog (ISPA) Device

SMD1108
Preliminary
REGISTER PARTITIONING
The registers have been divided into two main functional
blocks. The Configuration registers (from 0x80 through
0x95) are the primary setup registers that define the
SMD1108 for its specific application. These registers can
Reg. #
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
Reg. Name
Channel configuration
Address configuration
V_REF configuration
Timers 1
Timers 2
Quick trip
Healthy/Fault configuration
Healthy pin configuration
Healthy pin configuration
Fault pin configuration
Fault pin configuration
Fault mask
Fault mask
Reserved
Reserved
GPO register
Software reset
Status register
Status register
Reserved
Reserved
Fault latch
Fault latch
Reg. Type
Configuration
Registers
GFS Register
GFS Register
be (1) left open for both Read and Write operations, (2)
locked for Write but open for Read, or (3) totally blocked
for both .
The balance of the registers (the GSF registers) will
frequently be used during system operation, so the lock
combinations are more flexible. They can be (1) locked
for Read and Writes, (2) open for Read and Write but
excluding the configuration registers, (3) Read all regis-
ters but Write GSF only, or (4) Read and Write all
registers.
The organization, bit patterns and functions of the regis-
ters are illustrated in Tables 6 through 33.
Registers 80 through 83 set the under-voltage threshold
for the selected channel: CH4 through CH7. The register
value is determined by subtracting 0.9V from the desired
threshold, dividing the result by 0.02 and converting that to
a hexadecimal value.
The formula is (UV_TH – 0.9) / 0.02 = Decimal value (convert
to hexadecimal).
For example, if the UV threshold is to be 4.6V:
(4.6 – 0.9) / 0.02 = 185DEC = B9HEX
2052 Table05 1.0
Table 5. Register Address Map
14
2052 2.0 10/05/01
SUMMIT MICROELECTRONICS, Inc.