SMD1108 Datasheet, PDF (12/29 Pages) Summit Microelectronics, Inc. – 8-Channel Auto-Monitor ADC In System Programmable Analog (ISPA) Device

SMD1108
Preliminary
REGISTERS
REGISTER READ/WRITE
The registers are read and written using the same 2-wire
bus as the memory. The Configuration Registers and the
GFS Registers are written as shown in Figure 5. Reads
of the registers must be executed like a random Read
operation. That is, a dummy write must be issued in order
to set the address pointer for the following Read.
A
A
A
A A A C Register Address C Configuration C
1 0 1 1 2 1 0 W K 80 thru 9F
K Register Data K
S
S
T
T
A
O
R
2052 Fig05 1.0 P
T
Figure 5. Writing to the Configuration Registers
The Limits Registers for channels 0 through 3 are located
at the top of the ADC address space and utilize the 1001
DTI. Unlike the configuration registers that are limited to
single byte Writes or Reads, the ADC limit registers can
be written in page mode. The example In Figure 6 shows
two byte Writes to configure the CH0 Lower Limit.
Register Address
A
F0:
A
A
AAA C
C
DDC
1 0 0 1 2 1 0 WK 1 1 1 1 0 0 0 0 K x x x x x x 9 8 K
S
S
T
T
A
O
R
P
T
Register Address
A
F1:
A
A
AAA C
CD D D DD D D D C
1 0 0 1 2 1 0 WK 1 1 1 1 0 0 0 1 K 7 6 5 4 3 2 1 0 K
S
S
T
T
A
O
R
2052 Fig06 1.0 P
T
Even though the ADC cannot be written, performing
commanded conversions (non-auto-monitor mode) re-
quires a dummy Write operation to select the proper
channel and indicate the type of conversion process that
is being requested. The sequence would be: address the
device using 1001 as the DTI followed by the bus address
and a write bit. The next byte contains the conversion
process requested and the channel or channel group to be
converted.
Single Channel Conversion
The single channel Read allows the host to perform
manual conversions on a single channel. The state of bits
CH2, CH1 and CH0 selects one-of-eight channels. Read-
ing DTI 1001 will return the converted data. If the host
continues clocking SCL without an interim Stop command
the SMD1108 will continue conversions on the selected
channel and output the data as clocked. See the timing
sequence diagrams in Figure 7.
Multi-Channel Conversion: 4
Command 001 will configure the channel conversion such
that the MUX will switch channels 0 through 3 sequentially.
Multi-Channel Conversion: 8
Command 011 will configure the channel conversion such
that the MUX will switch channels 0 through 7 sequentially.
Differential Conversion
In order to provide a very accurate current sense the
SMD1108 can perform a differential conversion on a
selected CHx/OCx input combination. This is limited to
channels 4 through 7 and their corresponding OC inputs.
The measurement provides the differential voltage be-
tween the input channels (VCC0/CH4 to VCC3/CH7) and the
over-current sense inputs (OC0 to OC3). The result is
that differential noise is rejected and an accurate voltage
drop across the sense resistor is measured.
Figure 6. Writing to the Limits Registers
7
6
5
4
3
2
1
0 Bit
CMD
CH2 CH1 CH0
Function
0
0
0
CH2 CH1 CH0
Single channel read mode
0
0
1
x
x
x Continuous read mode 1
0
1
1
x
Continuous read mode 2
1
0
0
1
CH1 CH0
Differential conversion
Table 3. Command/Address Byte
2052 Table03 1.0
12
2052 2.0 10/05/01
SUMMIT MICROELECTRONICS, Inc.