SMD1108 Datasheet, PDF (16/29 Pages) Summit Microelectronics, Inc. – 8-Channel Auto-Monitor ADC In System Programmable Analog (ISPA) Device

SMD1108
Preliminary
Registers 88 and 89 provide selective enabling of the
channels and the channels’ functions. When channels 0
through 3 are enabled any out-of-limit condition will acti-
vate the LIM_IRQ# and SMB_ALERT# outputs. Channels 4
through 7 are more complex in that they are inputs to three
instant action measurements: under-voltage, over-volt-
age and over-current. Each one of these measurements
can be enabled on a channel by channel basis to activate
one of the three potential output reactions.
7
x
OV3
(CH7)
6
x
OV2
(CH6)
5
x
OV1
(CH5)
4
3
2
1
0
Function
x
UV3 UV2 UV1 UV0 A "1" enables the channel; an UV
(CH7) (CH6) (CH5) (CH4) condition will cause a RESET.
OV0
(CH4)
x
x
x
x
A "1" enables the channel; an OV
condition will cause an OV_IRQ.
Table 14. Register 88 Channel Enable — Part 1
2052 Table14 1.0
7
6
5
4
3
2
1
0
Function
x
OC3
(CH7)
x
OC2
(CH6)
x
OC1
(CH5)
x
LIM3
(CH3)
LIM2
(CH2)
LIM1
(CH1)
LIM0
(CH0)
A "1" enables the channel; an out-of-
limit condition will cause a LM_IRQ#
and a SMB_ALERT.
OC0
(CH4)
x
x
x
A "1" enables the channel; an over-
x current condition will cause an
OC_IRQ#.
2052 Table15 1.1
Table 15. Register 89 Channel Enable — Part 2
Register 8A controls access to the SMD1108 with regard
to the 2-wire interface and the function blocks that are
accessed through the 2-wire bus.
7
6
Reg. Access
x
x
0
0
0
1
1
0
1
1
5
ACK
x
0
1
x
x
x
x
4
3
2
1
0 Bits
Device Device
Type Address
CE
x
x
Function
0
x
x CE# input active low
x
1
x
x CE# input active high
x
0
x
x
x
Responds to address pin biased
address only
1
x
x
x Responds to any bus address
0
x
x
x
x EEPROM responds to 1010
1
x
x
x
x EEPROM responds to 1110
x
x
x
x
x ACK and access to DTI 1010
x
x
x
x
x No ACK/ no access to DTI 1010
x
x
x
x
x All registers locked: no read, no write
Read and write GFS registers only (98
x
x
x
x
x through 9F). All configuration registers
locked.
x
x
x
x
x Read all registers. Wrilte GFS registers.
x
x
x
x
x Read and write all registers
Table 16. Register 8A Slave Address Configuration
2052 Table16 1.0
16
2052 2.0 10/05/01
SUMMIT MICROELECTRONICS, Inc.