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| CD00001237 Datasheet, PDF (86/105 Pages) STMicroelectronics – 8-bit MCUs with A/D converter | |||
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ST6215C ST6225C
11.9 CONTROL PIN CHARACTERISTICS
11.9.1 Asynchronous RESET Pin
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ 1)
Max
Unit
VIL
Input low level voltage 2)
VIH Input high level voltage 2)
Vhys Schmitt trigger voltage hysteresis 3)
RON Weak pull-up equivalent resistor 4)
RESD ESD resistor protection
tw(RSTL)out Generated reset pulse duration
th(RSTL)in External reset pulse hold time 5)
tg(RSTL)in Filtered glitch duration 6)
0.7xVDD
200
400
VIN=VSS
VDD=5V
VDD=3.3V
150
300
350
730
VIN=VSS
VDD=5V
VDD=3.3V
2.8
External pin or
internal reset sources
0.3xVDD
900
1900
V
mV
kΩ
kΩ
tCPU
μs
μs
ns
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The RON pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results,
not tested in production.
5. All short pulse applied on RESET pin with a duration below th(RSTL)in can be ignored.
6. The reset network protects the device against parasitic resets, especially in a noisy environment.
7. The output of the external reset circuit must have an open-drain output to drive the ST6 reset pad. Otherwise the device
can be damaged when the ST6 generates an internal reset (LVD or watchdog).
Figure 69. Typical RON vs VDD with VIN=VSS
Ron [Kohm]
1000
900
800
700
600
500
400
300
200
100
3
Ta=-40°C
Ta=25°C
Ta=95°C
Ta=125°C
4
5
6
VDD [V]
86/105
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