CD00001237 Datasheet, PDF (52/105 Pages) STMicroelectronics – 8-bit MCUs with A/D converter

ST6215C ST6225C
8-BIT TIMER (Cont’d)
9.2.7 Register Description
PRESCALER COUNTER REGISTER (PSCR)
Address: 0D2h - Read/Write
Reset Value: 0111 1111 (7Fh)
7
0
PSCR PSCR PSCR PSCR PSCR PSCR PSCR PSCR
7
6
5
4
3
2
1
0
Bit 7 = PSCR7: Not used, always read as “0”.
Bits 6:0 = PSCR[6:0] Prescaler LSB.
ETI=0 the timer interrupt is disabled. If ETI=1 and
TMZ=1 an interrupt request is generated.
0: Interrupt disabled (reset state)
1: Interrupt enabled
Bit 5 = TOUT Timer Output Control.
When low, this bit selects the input mode for the
TIMER pin. When high the output mode is select-
ed.
0: Input mode (reset state)
1: Output mode, the TIMER pin is configured as
push-pull output
TIMER COUNTER REGISTER (TCR)
Address: 0D3h - Read / Write
Reset Value: 1111 1111 (FFh)
7
Bit 4 = DOUT Data Output.
Data sent to the timer output when TMZ is set high
(output mode only). Input mode selection (input
mode only).
0
TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
Bits 7:0 = TCR[7:0] Timer counter bits.
TIMER STATUS CONTROL REGISTER (TSCR)
Address: 0D4h - Read/Write
Reset Value: 0000 0000 (00h)
7
0
TMZ ETI TOUT DOUT PSI PS2 PS1 PS0
Bit 7 = TMZ Timer Zero bit.
A low-to-high transition indicates that the timer
count register has underflowed. It means that the
TCR value has changed from 00h to FFh.
This bit must be cleared by user software.
0: Counter has not underflowed
1: Counter underflow occurred
Bit 6 = ETI Enable Timer Interrupt.
When set, enables the timer interrupt request. If
Bit 3 = PSI: Prescaler Initialize bit.
Used to initialize the prescaler and inhibit its count-
ing. When PSI=“0” the prescaler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescal-
er is enabled to count downwards. As long as
PSE=“1” both counter and prescaler are not run-
ning
0: Counting disabled
1: Counting enabled
Bits 1:0 = PS[2:0] Prescaler Mux. Select.
These bits select the division ratio of the prescaler
register.
Table 13. Prescaler Division Factors
PS2
PS1
PS0 Divided by
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
Table 14. 8-Bit Timer Register Map and Reset Values
Address
(Hex.)
0D2h
0D3h
0D4h
Register Label
PSCR
Reset Value
TCR
Reset Value
TSCR
Reset Value
7
6
5
PSCR7
0
TCR7
1
TMZ
0
PSCR6
1
TCR6
1
ETI
0
PSCR5
1
TCR5
1
TOUT
0
4
PSCR4
1
TCR4
1
DOUT
0
3
PSCR3
1
TCR3
1
PSI
0
2
PSCR2
1
TCR2
1
PS2
0
1
PSCR1
1
TCR1
1
PS1
0
0
PSCR0
1
TCR0
1
PS0
0
52/105
1