CD00001237 Datasheet, PDF (42/105 Pages) STMicroelectronics – 8-bit MCUs with A/D converter

ST6215C ST6225C
I/O PORTS (Cont’d)
8.5 REGISTER DESCRIPTION
DATA REGISTER (DR)
Port x Data Register
DRx with x = A, B or C.
Addresses 0C0h, 0C1h and 0C2h- Read/Write
Bits 7:0 = DDR[7:0] Data direction register bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
Reset Value: 0000 0000 (00h)
7
0
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
Bits 7:0 = DR[7:0] Data register bits.
Reading the DR register returns either the DR reg-
ister latch content (pin configured as output) or the
digital value applied to the I/O pin (pin configured
as input).
Caution: In input mode, modifying this register will
modify the I/O port configuration (see Table 8).
Do not use the Single bit instructions on I/O port
data registers. See (Section 8.2.5).
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
DDRx with x = A, B or C.
Addresses: 0C4h, 0C5h and 0C6h - Read/Write
Reset Value: 0000 0000 (00h)
7
0
DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0
OPTION REGISTER (OR)
Port x Option Register
ORx with x = A, B or C.
Addresses: 0CCh, 0CDh and 0CEh - Read/Write
Reset Value: 0000 0000 (00h)
7
0
OR7 OR6 OR5 OR4 OR3 OR2 OR1 OR0
Bits 7:0 = OR[7:0] Option register bits.
The OR register allows to distinguish in output
mode if the push-pull or open drain configuration is
selected.
Output mode:
0: Open drain output(with P-Buffer deactivated)
1: Push-pull Output
Input mode: See Table 8.
Each bit is set and cleared by software.
Caution: Modifying this register, will also modify
the I/O port configuration in input mode. (see Ta-
ble 8).
Table 10. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Reset Value
of all I/O port registers
0
0
0
0
0
0
0
0
0C0h DRA
0C1h DRB
MSB
LSB
0C2h DRC
0C4h DDRA
0C5h DDRB
MSB
LSB
0C6h DDRC
0CCh ORA
0CDh ORB
MSB
LSB
0CEh ORC
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