CD00001237 Datasheet, PDF (12/105 Pages) STMicroelectronics – 8-bit MCUs with A/D converter

ST6215C ST6225C
MEMORY MAP (Cont’d)
Table 2. Hardware Register Map
Address
080h
to 083h
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0C8h
0C9h
0CAh
0CBh
0CCh
0CDh
0CEh
Block
CPU
I/O Ports
I/O Ports
CPU
ROM
I/O Ports
Register
Label
Register Name
X,Y,V,W
DRA ^{1) 2) 3)}
DRB ^{1) 2) 3)}
DRC ^{1) 2) 3)}
DDRA ²⁾
DDRB ²⁾
DDRC ²⁾
IOR
DRWR
X,Y index registers
V,W short direct registers
Port A Data Register
Port B Data Register
Port C Data Register
Reserved (1 Byte)
Port A Direction Register
Port B Direction Register
Port C Direction Register
Reserved (1 Byte)
Interrupt Option Register
Data ROM Window register
ORA ²⁾
ORB ²⁾
ORC ²⁾
Reserved (2 Bytes)
Port A Option Register
Port B Option Register
Port C Option Register
Reset
Status
Remarks
xxh
R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
xxh
Write-only
xxh
Write-only
00h R/W
00h R/W
00h R/W
0CFh
Reserved (1 byte)
0D0h
0D1h
ADC
ADR
ADCR
A/D Converter Data Register
A/D Converter Control Register
xxh
Read-only
40h Ro/Wo
0D2h
0D3h
0D4h
Timer1
PSCR
TCR
TSCR
Timer 1 Prescaler Register
Timer 1 Counter Register
Timer 1 Status Control Register
7Fh _R/W
0FFh _R/W
00h
R/W
0D5h
to 0D7h
Reserved (3 Bytes)
0D8h
Watchdog
Timer
WDGR
Watchdog Register
0FEh R/W
0D9h
to 0FEh
Reserved (38 Bytes)
0FFh
CPU
A
Accumulator
xxh
R/W
Legend:
x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s)
in the register.
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always be kept at their reset value.
3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured
in input mode (refer to Section 8 "I/O PORTS" on page 38 for more details).
12/105
1