CD00001237 Datasheet, PDF (66/105 Pages) STMicroelectronics – 8-bit MCUs with A/D converter

ST6215C ST6225C
OPERATING CONDITIONS (Cont’d)
11.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for V_DD, f_OSC, and T_A.
Symbol
Parameter
Conditions
Min Typ ¹⁾ Max Unit
V_IT+
V_IT-
V_hys
Vt_POR
t_g(VDD)
Reset release threshold
(V_DD rise)
Reset generation threshold
(V_DD fall)
LVD voltage threshold hysteresis
V_DD rise time rate ²⁾
Filtered glitch delay on V_DD ³⁾
V_IT+-V_IT-
Not detected by the LVD
3.9
4.1
4.3
V
3.6
3.8
4
50
300 700 mV
mV/s
30
ns
Notes:
1. LVD typical data are based on T_A=25°C. They are given only as design guidelines and are not tested.
2. The minimum V_DD rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.
3. Data based on characterization results, not tested in production.
Figure 39. LVD Threshold Versus V_DD and f_OSC³⁾
f_OSC [MHz]
DEVICE UNDER8
RESET
IN THIS AREA ₄
0
2.5
3
3.5 ^{VIT-≥3.6} 4
4.5
5
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONAL AREA
SUPPLY
VOLTAGE [V]
5.5
6
Figure 40. Typical LVD Thresholds Versus Figure 41. Typical LVD thresholds vs.
Temperature for OTP devices
Temperature for ROM devices
Thresholds [V]
4.2
4
VV_Id_Td₊ up
3.8
V_{VIdTd- down}
3.6
-40°C
25°C
95°C
T [°C]
125°C
Thresholds [V]
4.2
4
VV_ITd₊d up
3.8
V_{VITd-d down}
3.6
-40°C
25°C
95°C
T [°C]
125°C
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