LSM320HAY30 Datasheet, PDF (21/42 Pages) STMicroelectronics – MEMS motion sensor module: 3D digital accelerometer and 2D pitch and yaw analog gyroscope

LSM320HAY30
Digital interfaces
6.1.1
I²C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a high to low transition on the data line while the SCL line is held high. After this
has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the 8th bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.
The Slave ADdress (SAD) associated with the LSM320HAY30 is 001100xb. The SDO/SA0
pad can be used to modify the least significant bit of the device address. If the SA0 pad is
connected to voltage supply, LSb is ‘1’ (address 0011001b), otherwise if the SA0 pad is
connected to ground, the LSb value is ‘0’ (address 0011000b). This solution permits
connecting and addressing two different accelerometers to the same I²C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I²C embedded in the LSM320HAY30 behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent. Once a
slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the
7 LSb represent the actual register address while the MSB enables address auto-increment.
If the MSb of the SUB field is ‘1’, the SUB (register address) is automatically incremented to
allow multiple data read/write.
The slave address is completed with a read/write bit. If the bit was ‘1’ (read), a repeated
START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’
(write) the master transmits to the slave with direction unchanged. Table 9 explains how the
SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Table 9. SAD+Read/Write patterns
Command
SAD[6:1]
SAD[0] = SA0
Read
001100
0
Write
001100
0
Read
001100
1
Write
001100
1
R/W
SAD+R/W
1
00110001 (31h)
0
00110000 (30h)
1
00110011 (33h)
0
00110010 (32h)
Table 10.
Master
Slave
Transfer when master is writing one byte to slave
ST
SAD + W
SUB
DATA
SAK
SAK
SP
SAK
Doc ID 16917 Rev 1
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