LAN9118_07 Datasheet, PDF(94/129 Page) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

LAN9118_07 Datasheet, PDF (94/129 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

◁

INDEX

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

Datasheet

Table 5.6 LAN9118 MAC CSR Register Map

MAC CONTROL AND STATUS REGISTERS

SYMBOL

MAC_CR

ADDRH

ADDRL

HASHH

HASHL

MII_ACC

MII_DATA

FLOW

VLAN1

VLAN2

WUFF

WUCSR

MAC Control Register

MAC Address High

MAC Address Low

Multicast Hash Table High

Multicast Hash Table Low

MII Access

MII Data

Flow Control

VLAN1 Tag

VLAN2 Tag

Wake-up Frame Filter

Wake-up Control and Status

DEFAULT

00040000h

0000FFFFh

FFFFFFFFh

00000000h

5.4.1 MAC_CRâMAC Control Register

Offset:

Default Value:

00040000h

Attribute:

Size:

R/W

32 bits

This register establishes the RX and TX operation modes and controls for address filtering and packet

filtering.

BITS

30-24

DESCRIPTION

Receive All Mode (RXALL). When set, all incoming packets will be received and passed on to the

address filtering Function for processing of the selected filtering mode on the received frame. Address

filtering then occurs and is reported in Receive Status. When reset, only frames that pass Destination

Address filtering will be sent to the Application.

Reserved

Disable Receive Own (RCVOWN). When set, the MAC disables the reception of frames when the

MII TX_EN signal is asserted. The MAC blocks the transmitted frame on the receive path. When reset,

the MAC receives all packets the PHY gives, including those transmitted by the MAC.This bit should

be reset when the Full Duplex Mode bit is set.

Reserved

Revision 1.3 (05-31-07)

DATASHEET

SMSC LAN9118

▷