LAN9118_07 Datasheet, PDF (20/129 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Table 2.5 System and Power Signals (continued)
Datasheet
PIN
NO.
3,65
1,66
7
4
8
11
NAME
SYMBOL
BUFFER NUM
TYPE
PINS
DESCRIPTION
Core Voltage
VDD_CORE
P
Decoupling
2
1.8 V from internal core regulator.
Both pins must be connected
together externally and then tied to a
10uF 0.1-Ohm ESR capacitor, in
parallel with a 0.01uF capacitor to
Ground next to each pin. See
Note 2.1
Core Ground
GND_CORE
P
2
Ground for internal digital logic
PLL Power
VDD_PLL
P
1
1.8V Power from the internal PLL
regulator. This external pin must be
connected to a 10uF 0.1-Ohm ESR
capacitor, in parallel with a 0.01uF
capacitor to Ground. See Note 2.1
PLL Ground
VSS_PLL
P
1
GND for the PLL
Reference Power
VDD_REF
P
1
Connected to 3.3v power and used
as the reference voltage for the
internal PLL
Reference Ground
VSS_REF
P
1
Ground for internal PLL reference
voltage
Note 2.1
Please refer to the SMSC application note AN 12.5 titled “Designing with the LAN9118 -
Getting Started”. It is also important to note that this application note applies to the whole
SMSC LAN9118 family of Ethernet controllers. However, subtle differences may apply.
2.1
Buffer Types
TYPE
I
IS
O12
OD12
IO8
OD8
O8
PU
PD
AI
AO
Revision 1.3 (05-31-07)
Table 2.6 Buffer Types
Input pin
DESCRIPTION
Schmitt triggered Input
Output with 12mA sink and 12mA source
Open-drain output with 12mA sink
I/O with 8mA symmetrical drive
Open-drain output with 8mA sink
Output 8mA symmetrical drive
50uA (typical) internal pull-up
50uA (typical) internal pull-down
Analog input
Analog output
20
DATASHEET
SMSC LAN9118