LAN9118_07 Datasheet, PDF (116/129 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 6.4 PIO Burst Read Timing
SYMBOL DESCRIPTION
MIN
t_csh
nCS, nRD Deassertion Time
13
t_csdv
nCS, nRD Valid to Data Valid
t_acyc
Address Cycle Time
45
t_asu
Address Setup to nCS, nRD valid
0
t_adv
Address Stable to Data Valid
t_ah
Address Hold Time
0
t_don
Data Buffer Turn On Time
0
t_doff
Data Buffer Turn Off Time
t_doh
Data Output Hold Time
0
TYP
MAX UNITS
ns
30
ns
ns
40
ns
ns
7
ns
ns
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
6.4
RX Data FIFO Direct PIO Reads
In this mode the upper address inputs are not decoded, and any read of the LAN9118 will read the
RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is
normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9118. Timing is
identical to a PIO read, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Timing for 16-bit and 32-bit Direct PIO Read cycles is identical with the exception that D[31:16] is not
driven during a 16-bit read. Note that address lines A[2:1] are still used, and address bits A[7:3] are
ignored.
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
Figure 6.3 RX Data FIFO Direct PIO Read Cycle Timing
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Revision 1.3 (05-31-07)
116
DATASHEET
SMSC LAN9118