LAN9118_07 Datasheet, PDF (78/129 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
BITS DESCRIPTION
16-19
15-14
TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values
to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the
space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the
remaining space specified by TX_FIF_SZ. The minimum size of the TX
FIFOs is 2KB (TX data and status combined). The TX data FIFO is used for
both TX data and TX commands.
The RX status and data FIFOs consume the remaining space, which is
equal to 16KB – TX_FIF_SIZ. See Section 5.3.9.1, "Allowable settings for
Configurable FIFO Memory Allocation," on page 79 for more information.
Reserved
13-12
Threshold Control Bits (TR). These control the transmit threshold values
the MIL should use. These bits are used when the SF bit is reset. The host
can program the Transmit threshold by setting these bits. The intent is to
allow the MIL to transfer data to the final destination only after the threshold
value is met.
In 10Mbps mode (TTM = 1) the threshold is set as follows:
TYPE
R/W
RO
R/W
DEFAULT
5h
-
00
[13]
[12]
0
0
0
1
1
0
1
1
Threshold (DWORDS)
012h
018h
020h
028h
In 100Mbps mode (TTM = 0) the threshold is set by as follows:
[13]
[12]
0
0
0
1
1
0
1
1
Threshold (DWORDS)
020h
040h
080h
100h
11-3 Reserved
RO
-
2 32/16-bit Mode. When set, the LAN9118 is set for 32-bit operation. When
RO
-
clear, it is configured for 16-bit operation. This field is the value of the
D32/nD16 strap.
1 Soft Reset Time-out (SRST_TO). If a software reset is attempted when the
RO
0
internal PHY is not in the operational state (RX_CLK and TX_CLK running),
the reset will not complete and the soft reset operation will time-out and this
bit will be set to a ‘1’. The host processor must correct the problem and
issue another soft reset.
Revision 1.3 (05-31-07)
78
DATASHEET
SMSC LAN9118