LAN9118_07 Datasheet, PDF (115/129 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 6.3 PIO Read Timing
SYMBOL DESCRIPTION
MIN
t_cycle
Read Cycle Time
45
t_csl
nCS, nRD Assertion Time
32
t_csh
nCS, nRD Deassertion Time
13
t_csdv
nCS, nRD Valid to Data Valid
t_asu
Address Setup to nCS, nRD Valid
0
t_ah
Address Hold Time
0
t_don
Data Buffer Turn On Time
0
t_doff
Data Buffer Turn Off Time
t_doh
Data Output Hold Time
0
TYP
MAX UNITS
ns
ns
ns
30
ns
ns
ns
ns
7
ns
ns
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
6.3
PIO Burst Reads
In this mode, performance is improved by allowing up to 8, DWORD read cycles, or 16, WORD read
cycles back-to-back. PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable
(nRD). Either or both of these control signals must go high between bursts for the period specified.
Timing for 16-bit and 32-bit PIO Burst Mode Read cycles is identical, with the exception that D[31:16]
are not driven during a 16-bit burst.
A[7:5]
A[4:1]
nCS, nRD
Data Bus
Figure 6.2 LAN9118 PIO Burst Read Cycle Timing
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
SMSC LAN9118
115
DATASHEET
Revision 1.3 (05-31-07)