LAN9118_07 Datasheet, PDF (15/129 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 2.1 Host Bus Interface Signals
PIN NO.
21-26,29-
33,36-40
NAME
Host Data High
43-46,49-
53,56-59,62-
64
12-18
Host Data Low
Host Address
92
Read Strobe
93
Write Strobe
94
Chip Select
72
Interrupt
Request
76
FIFO Select
SYMBOL
D[31:16]
D[15:0]
A[7:1]
nRD
nWR
nCS
IRQ
FIFO_SEL
BUFFER
#
TYPE PINS
DESCRIPTION
I/O8 (PD) 16 Bi-directional data port.
Note that Pull-down’s are disabled in
32 bit mode.
I/O8
16 Bi-directional data port.
IS
IS
IS
IS
O8/OD8
IS
7 7-bit Address Port. Used to select
Internal CSR’s and TX and RX FIFOs.
1 Active low strobe to indicate a read
cycle.
1 Active low strobe to indicate a write
cycle. This signal, qualified with nCS, is
also used to wakeup the LAN9118
when it is in a reduced power state.
1 Active low signal used to qualify read
and write operations. This signal
qualified with nWR is also used to
wakeup the LAN9118 when it is in a
reduced power state.
1 Programmable Interrupt request.
Programmable polarity, source and
buffer types.
1 When driven high all accesses to the
LAN9118 are to the RX or TX Data
FIFOs. In this mode, the A[7:3] upper
address inputs are ignored.
SPEED_SEL
0
1
SPEED
10MBPS
100MBPS
Table 2.2 Default Ethernet Settings
DEFAULT ETHERNET SETTINGS
DUPLEX
HALF-DUPLEX
HALF-DUPLEX
AUTO NEG.
DISABLED
ENABLED
SMSC LAN9118
15
DATASHEET
Revision 1.3 (05-31-07)