LAN9118_07 Datasheet, PDF (120/129 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
FIFO_SEL
A[2:1]
nCS, nWR
Data Bus
Figure 6.6 TX Data FIFO Direct PIO Write Timing
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
SYMBOL
t_cycle
t_csl
t_csh
t_asu
t_ah
t_dsu
t_dh
Table 6.8 TX Data FIFO Direct PIO Write Timing
DESCRIPTION
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
MIN
TYP
45
32
13
0
0
7
0
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The
cycle ends when either or both nCS and nWR are deasserted. They may be asserted and
deasserted in any order.
Revision 1.3 (05-31-07)
120
DATASHEET
SMSC LAN9118