LAN9118_07 Datasheet, PDF (70/129 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

BASE ADDRESS
+ OFFSET
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h - FCh
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Table 5.1 LAN9118 Direct Address Register Map (continued)
Datasheet
CONTROL AND STATUS REGISTERS
SYMBOL
FREE_RUN
RX_DROP
MAC_CSR_CMD
MAC_CSR_DATA
AFC_CFG
E2P_CMD
E2P_DATA
RESERVED
REGISTER NAME
Free Run Counter
RX Dropped Frames Counter
MAC CSR Synchronizer Command (MAC
CSR’s are indexed through this register)
MAC CSR Synchronizer Data
Automatic Flow Control Configuration
EEPROM command (The EEPROM is
indexed through this register)
EEPROM Data
Reserved for future use
DEFAULT
-
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
-
5.3.1 ID_REV—Chip ID and Revision
Offset:
50h
Size:
32 bits
This register contains the ID and Revision fields for this design.
BITS DESCRIPTION
31-16 Chip ID. This read-only field identifies this design
15-0 Chip Revision. This is the current revision of the chip.
TYPE
RO
RO
DEFAULT
0118h
0001h
Revision 1.3 (05-31-07)
70
DATASHEET
SMSC LAN9118