LAN9118_07 Datasheet, PDF(69/129 Page) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

LAN9118_07 Datasheet, PDF (69/129 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

◁

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

Datasheet

5.2.2

TX FIFO Ports

The TX data Path consists of two FIFOs, the TX status and data. The TX Status FIFO can be read

from two locations. The TX Status FIFO Port will perform a destructive read, thus âPoppingâ the data

from the TX Status FIFO. There is also the TX Status FIFO PEEK location. This location allows a non-

destructive read of the top (oldest) location of the FIFO.

The TX data FIFO is Write Only. It is aliased in 8 DWORD locations (16 WORD locations in 16-bit

mode) from the 20h offset to 3Ch offset. The host may write to any of the 8(16) locations since they

all access the same TX data FIFO location and perform the same function.

5.3

System Control and Status Registers

Table 5.1, "LAN9118 Direct Address Register Map", lists the registers that are directly addressable by

the host bus.

BASE ADDRESS

+ OFFSET

50h

54h

58h

5Ch

60h

64h

68h

6Ch

70h

74h

78h

7Ch

80h

84h

88h

8Ch

90h

94h

98h

Table 5.1 LAN9118 Direct Address Register Map

CONTROL AND STATUS REGISTERS

SYMBOL

ID_REV

Chip ID and Revision.

IRQ_CFG

INT_STS

INT_EN

RESERVED

BYTE_TEST

FIFO_INT

RX_CFG

TX_CFG

HW_CFG

RX_DP_CTL

RX_FIFO_INF

TX_FIFO_INF

PMT_CTRL

GPIO_CFG

GPT_CFG

GPT_CNT

RESERVED

WORD_SWAP

Main Interrupt Configuration

Interrupt Status

Interrupt Enable Register

Reserved for future use

Read-only byte order testing register

FIFO Level Interrupts

Receive Configuration

Transmit Configuration

Hardware Configuration

RX Datapath Control

Receive FIFO Information

Transmit FIFO Information

Power Management Control

General Purpose IO Configuration

General Purpose Timer Configuration

General Purpose Timer Count

Reserved for future use

WORD SWAP Register

DEFAULT

See âID_REVâ

Chip ID and

Revisionâ on

page 70.

00000000h

87654321h

48000000h

00000000h

00050000h

00000000h

00001200h

00000000h

0000FFFFh

00000000h

SMSC LAN9118

DATASHEET

Revision 1.3 (05-31-07)

▷