SIO10N268 Datasheet, PDF (91/251 Pages) SMSC Corporation – Advenced Notebook I/O for ISA or LPC Designs with X-Bus Interface for I/O, Memory, and FWH Emulation and Four Srial Ports

Advanced Notebook I/O for ISA or LPC Designs
Datasheet
8.7.8.12 Enhanced DUMPREG
The DUMPREG command is designed to support system run-time diagnostics and application software
development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR
MODE command the eighth byte of the DUMPREG command has been modified to contain the additional
data from these two commands.
8.7.8.13 Compatibility
The SIO10N268 was designed with software compatibility in mind. It is a fully backwards- compatible
solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for
compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a
hardware reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2
Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the
system BIOS.
8.8
Serial Port (UART)
The SIO10N268 incorporates four full function UARTs. They are compatible with the 16450, the 16450
ACE registers and the 16C550A. The UARTS perform serial-to-parallel conversion on received characters
and parallel-to-serial conversion on transmit characters. The data rates are independently programmable
from 460.8K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop
bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a programmable
baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The
UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration Registers for
information on disabling, power down and changing the base address of the UARTs. The interrupt from
a UART is enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic "0" disables
that UART's interrupt. The second UART also supports IrDA 1.2 (4Mbps), HP-SIR, ASK-IR and Consumer
IR infrared modes of operation.
8.8.1 Register Description
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial
ports are defined by the configuration registers (see Configuration section). The Serial Port registers are
located at sequentially increasing addresses above these base addresses. The SIO10N268 contains two
serial ports, each of which contain a register set as described below.
DLAB*
0
0
0
X
X
X
X
X
X
X
1
1
Table 8.33 - Addressing the Serial Port
A2
A1
A0
REGISTER NAME
0
0
0 Receive Buffer (read)
0
0
0 Transmit Buffer (write)
0
0
1 Interrupt Enable (read/write)
0
1
0 Interrupt Identification (read)
0
1
0 FIFO Control (write)
0
1
1 Line Control (read/write)
1
0
0 Modem Control (read/write)
1
0
1 Line Status (read/write)
1
1
0 Modem Status (read/write)
1
1
1 Scratchpad (read/write)
0
0
0 Divisor LSB (read/write)
0
0
1 Divisor MSB (read/write
SMSC SIO10N268
Page 91
DATASHEET
Rev. 0.5 (03-24-05)