SIO10N268 Datasheet, PDF (224/251 Pages) SMSC Corporation – Advenced Notebook I/O for ISA or LPC Designs with X-Bus Interface for I/O, Memory, and FWH Emulation and Four Srial Ports

PCI_CLK
LFRAME#
LAD[3:0]#
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Start C+D CHL Size Data
TAR
Sync=0101
L1
TAR
NOTE: L1=Sync of 0000
Figure 12.11 - DMA Read (First Byte)
12.4 X-Bus Timing (LPC Mode Only)
12.4.1 X-Bus I/O Timing
NOTE: The following timing values are based on a 33MHz PCI clock. Timing values will vary with variations in the
PCI clock frequency.
12.4.1.1 X-Bus I/O Read Timing
Ax, nXCSx
nXRD
Data
t3
t1
t2
t5
t4
Valid
Figure 12.12 – X-Bus I/O Read Timing
NAME
t1
t2
DESCRIPTION
nXCS active to nXRD active
nXRD active to nXRD inactive
t3
nXRD inactive to nxCS inactive
t4
Data valid to nXRD inactive
t5
nXRD inactive to data invalid
MIN
TYP
100
A: 180
B: 300
C: 420
D: 540
40
20
0
MAX
190
UNITS
ns
ns
ns
ns
ns
NOTE: Cases A-D for t2 correspond to the different pulse width options for the X-Bus read strobe. See the Pulse
Width Selection bits located in the X-Bus I/O Select Register at offset CR52.
Rev. 0.5 (03-24-05)
Page 226
DATASHEET
SMSC SIO10N268