SIO10N268 Datasheet, PDF (34/251 Pages) SMSC Corporation – Advenced Notebook I/O for ISA or LPC Designs with X-Bus Interface for I/O, Memory, and FWH Emulation and Four Srial Ports

Chapter 8
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Functional Description
8.1
Super I/O Registers
The address map, shown below in Table 8.1, shows the addresses of the different blocks of the Super I/O
immediately after power up. The base addresses of the FDC, serial and parallel ports, runtime register
block and configuration register block can be moved via the configuration registers. Some addresses are
used to access more than one register.
8.2 Host Processor Interface (LPC or ISA)
The host processor interface is selectable by the LPC_ISA pin (pin 54). The LPC_ISA pin may be
connected directly to VCC to select ISA mode (a pull-up is not recommended, but one less than 1k ohms
can be used). It can either be left unconnected or connected to ground to select LPC Mode. Mode
dependent interface pins are shown in the table located in section Chapter 4 Description of Pin Functions
on page 18.
The host processor communicates with the SIO10N268 through a series of read/write registers via the host
processor interface (LPC or ISA). The port addresses for these registers are shown in Table 8.1. Register
access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide.
Table 8.1 - Super I/O Block Addresses
ADDRESS
Base+(0-5) and +(7)
Base+(0-7)
Base1+(0-7)
Base2+(0-7)
Base+(0-7)
Base+(0-7)
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
Base + (0-F)
Base + (0-1)
Base +(0)
Base +(0)
BLOCK NAME
Floppy Disk
Serial Port Com 1
Serial Port Com 2
Serial Port Com 3
Serial Port Com 4
Parallel Port
SPP
EPP
ECP
ECP+EPP+SPP
Runtime Registers
Configuration
X-Bus
Chip Select 1 (nXCS1)
Chip Select 2 (nXCS2)
Note 8.1 Refer to the configuration register descriptions for setting the base address.
NOTES
IR Support
FIR and CIR
Rev. 0.5 (03-24-05)
Page 34
DATASHEET
SMSC SIO10N268