SIO10N268 Datasheet, PDF (49/251 Pages) SMSC Corporation – Advenced Notebook I/O for ISA or LPC Designs with X-Bus Interface for I/O, Memory, and FWH Emulation and Four Srial Ports

Advanced Notebook I/O for ISA or LPC Designs
Datasheet
The following figure shows the X-bus interface in mode 3.
LPC
Address
12
LPC Data
LPC
R/W Command
I/O
Read-
8
nXRD
Active
I/O
Write-
nXWR
Active
8-bit
Data
Bus
X-Bus CS1 Base
Address Configuration
Register
Disable
X-Bus CS2 Base
Address Configuration
Register
Disable
10-bit Address Comparator
(Bits[15:12]=0 & Bit[0]=0)
10-bit Address Comparator
(Bits[15:12]=0 & Bit[0]=0)
Alternate Pin Functions
(GP22/IRMODE/IRRX3)
nXCS1
a
Alternate
Function
Mux
nXCS2
XA2
a - Alternate Function Select bits
Figure 8.6 - X-Bus Interface, Mode 3
8.5.2 Memory Cycles
All Firmware Hub and LPC memory cycles that have been accepted and decoded by the LPC interface are
forwarded to the X-Bus interface and are enabled on nXCS0. See section 8.4.2 FWH and LPC Memory
Addressing for a description of the memory cycles forwarded to the X-Bus interface. This interface is
capable of accessing up to 2MB (16Mbit) of external flash memory in 8-bit words only.
The X-Bus Chip Select 0 Register at offset CR53 is used to configure access for memory cycles to the X-
Bus interface. On a VCC POR and Hard Reset this chip select defaults to be enabled. Chip select 0
(nXCS0) may be disabled by setting bit[7] of the X-Bus Chip Select 0 Register to ‘0’.
SMSC SIO10N268
Page 49
DATASHEET
Rev. 0.5 (03-24-05)