SIO10N268 Datasheet, PDF (31/251 Pages) SMSC Corporation – Advenced Notebook I/O for ISA or LPC Designs with X-Bus Interface for I/O, Memory, and FWH Emulation and Four Srial Ports

Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Chapter 7 Power Functionality
The SIO10N268 has two power planes: VCC and VTR.
7.1
VCC Power
The SIO10N268 is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the Operational
Description Section and the Maximum Current Values subsection.
7.2 VTR Support
The SIO10N268 requires a trickle supply (V_TR) to provide sleep current for the programmable wake-up
events in the PME interface when V_CC is removed. The VTR supply is 3.3 Volts (nominal). See the
Operational Description Section. The maximum VTR current that is required depends on the functions that
are used in the part. See Trickle Power Functionality subsection and the Maximum Current Values
subsection. If the SIO10N268 is not intended to provide wake-up capabilities on standby current, V_TR can
be connected to V_CC. The V_TR pin generates a V_TR Power-on-Reset signal to initialize these components.
NOTE:
If V_TR is to be used for programmable wake-up events when V_CC is removed, V_TR must be at its full
minimum potential at least 10 µs before V_CC begins a power-on cycle. When V_TR and V_CC are fully
powered, the potential difference between the two supplies must not exceed 500mV.
7.3 32.768 kHz Trickle Clock Input
The SIO10N268 utilizes a 32.768 kHz trickle input to supply a clock signal for the Watchdog Timer (WDT)
and LED blink function.
NOTE: LED1 has a VCC powered output pin and will only generate a signal when the device is powered by VCC.
LED2 has a VTR powered output pin and may be used under VTR power.
The SIO10N268 has two different methods of deriving a 32.768kHz signal:
ƒ From an external single-input clock source driven on the CLKI32 pin
ƒ From an internal PLL that divides down the14MHz clock input to make the 32kHz signal
If the 32kHz input clock is not used the CLKI32 pin must be grounded and the CLK32_PRSN bit should be
set to ‘1’. This bit in the configuration register block at register index CR1E determines whether the
internal 32KHz clock is derived from the CLKI32 pin or the 14MHz clock input. This clock input is used as
the clock source for the WDT and the LEDs. This register is powered by VTR and reset on a VTR POR.
Bit[0] (CLK32_PRSN) is defined as follows:
0=32kHz clock is connected to the CLKI32 pin (default)
1=32kHz clock is not connected to the CLKI32 pin (pin is grounded).
Bit 0 controls the source of the 32kHz (nominal) clock for the LED blink logic and the WDT. When the
external 32kHz clock is connected, bit[0] should be set to ‘0’ so that the external clock will be the source for
the LED blink logic and the WDT. When the external 32kHz clock is not connected, bit[0] should be set to
‘1’ so that an internal 32kHz clock source will be derived from the 14MHz clock for the LED blink logic and
the WDT.
SMSC SIO10N268
Page 31
DATASHEET
Rev. 0.5 (03-24-05)