SIO10N268 Datasheet, PDF (111/251 Pages) SMSC Corporation – Advenced Notebook I/O for ISA or LPC Designs with X-Bus Interface for I/O, Memory, and FWH Emulation and Four Srial Ports

Advanced Notebook I/O for ISA or LPC Designs
Datasheet
HOST
CONNECTOR
16
PIN NUMBER
63
STANDARD
nINIT
17
64
nSLCTIN
EPP
nRESET
nAddrstrb
ECP
nInit(1)
nReverseRqst(3)
nSelectIn(1,3)
(1) = Compatible Mode
(3) = High Speed Mode
NOTE:
For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This
document is available from Microsoft.
8.10.1 IBM XT/AT Compatible, Bi-Directional And EPP Modes
8.10.1.1 Data Port
ADDRESS OFFSET = 00H
The Data Port is located at an offset of '00H' from the base address. The data register is cleared at
initialization by RESET. During a WRITE operation, the Data Register latches the contents of the internal
data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports.
During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host
CPU.
8.10.1.2 Status Port
ADDRESS OFFSET = 01H
The Status Port is located at an offset of '01H' from the base address. The contents of this register are
latched for the duration of a read cycle. The bits of the Status Port are defined as follows:
BIT 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A
logic zero means that no time out error has occurred; a logic 1 means that a time out error has been
detected.
The means of clearing the TIMEOUT bit is controlled by the TIMEOUT_SELECT bit as follows. The
TIMEOUT_SELECT bit is located at bit 2 of CR21.
ƒ If the TIMEOUT_SELECT bit is cleared (‘0’), the TIMEOUT bit is cleared on the trailing edge of the
read of the EPP Status Register (default)
ƒ If the TIMEOUT_SELECT bit is set (‘1’), the TIMEOUT bit is cleared on a write of ‘1’ to the TIMEOUT
bit.
The TIMEOUT bit is cleared on PCI_RESET regardless of the state of the TIMEOUT_SELECT bit.
BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are
a low level.
BIT 3 nERR - nERROR
SMSC SIO10N268
Page 113
DATASHEET
Rev. 0.5 (03-24-05)