SI5110 Datasheet, PDF (9/26 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Table 5. AC Characteristics (Receiver PLL)
(V_DD = 1.8 V ±5%, T_A = –40°C to 85°C)
Parameter
Symbol
Test Condition
Jitter Tolerance
J_TOL(PP)
f = 600 Hz
f = 6000 kHz
f = 100 kHz
f = 1 MHz
Acquisition Time
T_AQ
Input Reference Clock Frequency RC_FREQ
REFRATE = 1
REFRATE = 0
Reference Clock Duty Cycle
RC_DUTY
Reference Clock Frequency
Tolerance
RC_TOL
Frequency Difference at which
LOL
Receive PLL goes out of Lock
(REFCLK compared to the
divided down VCO clock)
Frequency Difference at which
Receive PLL goes into Lock
(REFCLK compared to the
divided down VCO clock)
LOCK
Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998.
Table 6. AC Characteristics (Transmitter Clock Multiplier)
(V_DD = 1.8 V ±5%, T_A = –40°C to 85°C)
Parameter
Symbol
Test Condition
Jitter Generation
Jitter Transfer Bandwidth
J_GEN(rms)
J_BW
PRBS 23
BWSEL = 0
BWSEL = 1
Jitter Transfer Peaking
Acquisition Time
T_AQ
Input Reference Clock Frequency RC_FREQ
Valid REFCLK
REFRATE = 1
REFRATE = 0
Input Reference Clock Duty
Cycle
RC_DUTY
Input Reference Clock Frequency RC_TOL
Tolerance
Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998.
Si5110
Min Typ
15
30
1.5
3.0
1.5
3.0
0.15
0.3
—
—
—
155
—
78
40
50
–100
—
Max Unit
— UIpp
— UIpp
— UIpp
— UIpp
20
µs
167 MHz
83 MHz
60
%
100 ppm
TBD 600 1000 ppm
TBD 300 TBD ppm
Min
Typ
Max Unit
0.005 TBD UI_RMS
—
—
6
kHz
—
—
25
kHz
—
0.05
0.1
dB
—
—
20
µs
—
155
167 MHz
—
78
84 MHz
40
—
60
%
–100
—
100 ppm
Preliminary Rev. 0.41
9