SI5110 Datasheet, PDF (12/26 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5110
PhaseOffset
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Phase Offset is the sampling offset in degrees from the
center of the data eye, V_PHASE is the voltage applied to
the PHASEADJ pin, and VREF is reference voltage
output on the VREF pin. A positive phase offset will
adjust the sampling point to lead the default sampling
point in the center of the data eye, and a negative phase
offset will adjust the sampling point to lag the default
sampling point.
Data recovery using a sampling phase offset is disabled
by tieing the PHASEADJ input to the supply (VDD). This
forces a phase offset of 0^o to be used for data recovery.
Receiver Lock Detect
The Si5110 provides lock-detect circuitry that indicates
whether the PLL has achieved frequency lock with the
incoming data. This circuit compares the frequency of a
divided down version of the recovered clock with the
frequency of the supplied reference clock (REFCLK). If
the recovered clock frequency deviates from that of the
reference clock by the amount specified in Table 5 on
page 9, the PLL is declared out of lock, and the loss-of-
lock (RXLOL) pin is asserted. In this state, the PLL will
attempt to reacquire lock with the incoming data stream.
During reacquisition, the recovered clock frequency
(RXCLK1 and RXCLK2) will drift over a ±1000 ppm
range relative to the supplied reference clock. The
RXLOL output will remain asserted until the recovered
clock frequency is within the REFCLK frequency by the
amount specified in Table 5 on page 9.
Lock-to-Reference
In applications where it is desirable to maintain a stable
output clock during an alarm condition like loss-of-
signal, the lock-to-reference input (LTR) can be used to
force a stable output clock. When LTR is asserted, the
CDR is prevented from acquiring the data signal and the
CDR will lock the RXCLKOUT1 and RXCLKOUT2
outputs to the provided REFCLK. In typical applications,
the LOS output would be tied to the LTR input to force a
stable output clock.
Deserialization
The Si5110 uses a 1:4 demultiplexer to deserialize the
high speed input. The deserialized data is output on a 4-
bit parallel data bus, RXDOUT[3:0], synchronous with
the rising edge of RXCLK1. This clock output is derived
by dividing down the recovered clock by a factor of 4.
Serial Input to Parallel Output Relationship
The Si5110 provides the capability to select the order in
which the received serial data is mapped to the parallel
output bus RXDOUT[3:0]. The mapping of the receive
bits to the output data word is controlled by the
RXMSBSEL input. If RXMSBSEL is tied low, the first bit
received is output on RXDOUT0 and the following bits
are output in order on RXDOUT1 through RXDOUT3. If
RXMSBSEL is tied high, the first bit received is output
on RXDOUT3, and the following bits are output in order
on RXDOUT2 through RXDOUT0.
Auxiliary Clock Output
To support the widest range of system timing
configurations, a second clock output is provided on
RXCLK2. This output can be configured to provide a
clock equal to either the parallel output word rate or
1/4th the output word rate. The divide factor used to
generate RXCLK2 is controlled via the RXCLKDIV2
input as described in the Pin Description table. In
applications which do not use RXCLK2, this output can
be powered down by forcing the RSCLK2DSBL input
high.
Data Squelch
During some system error conditions, such as LOS, it
may be desirable to force the receive data output to
zero in order to avoid propagation of erroneous data
into the downstream processing circuitry. In these
applications, the Si5110 provides a data squelching
control input, RXSQLCH. When this input is active low,
the data on RXDOUT will be forced to 0. Data squelch is
disabled if the device is operating in diagnostic
loopback mode (DLBK = 0).
Transmitter
The transmitter consists of a low jitter, clock multiplier
unit (CMU) with a 4:1 serializer. The CMU uses a
phase-locked loop (PLL) architecture based on Silicon
Laboratories’ proprietary DSPLL^™ technology. This
technology is used to generate ultra-low jitter clock and
data outputs that provide significant margin to the
SONET/SDH specifications. The DSPLL architecture
also utilizes a digitally implemented loop filter that
eliminates the need for external loop filter components.
As a result, sensitive noise coupling nodes that typically
cause degraded jitter performance in crowded PCB
environments are removed.
The DSPLL also reduces the complexity and
performance requirements of reference clock
distribution strategies for OC-48/STM-16 optical port
cards. This is possible because the DSPLL provides
selectable wideband and narrowband loop filter settings
that allow the user to set the jitter attenuation
characteristics of the CMU to accommodate reference
clock sources that have a high jitter content. Unlike
traditional analog PLL implementations, the loop filter
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Preliminary Rev. 0.41