SI5110 Datasheet, PDF (21/26 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5110
Pin
Number(s)
D8
Name
RXMSBSEL
A4
RXREXT
A5
RXSQLCH
A3
SLICELVL
K7–8
K5–6
TXCLK4IN,
TXCLK4IN
TXCLK4OUT,
TXCLK4OUT
J8
TXCLKDSBL
E1, F1
TXCLKOUT,
TXCLKOUT
I/O Signal Level
Description
I
LVTTL
Data Bus Receive Order.
This determines the order of the received data bits on
the output bus.
For RXMSBSEL = 0, the first data bit received is out-
put on RXDOUT[0] and following data bits are output
on RDOUT[1] through RXDOUT[3].
For RXMSBSEL = 1, the first data bit is output on
RXDOUT[3] and following data bits are output on
RXDOUT[2] through RXDOUT[0].
External Bias Resistor.
This resistor is used by the receiver circuitry to estab-
lish bias currents within the device. This pin must be
connected to GND through a 3.09 kΩ (1%) resistor.
I
LVTTL
Data Squelch.
When this input is low the data on RXDOUT is forced
to 0. Set high for normal operation.
I
Slicing Level Adjustment.
Applying an analog voltage to this pin allows adjust-
ment of the slicing level applied to the input data eye.
Tieing this input high nominally sets the slicing offset
to 0.
I
LVDS
Differential Data Clock Input.
The rising edge of this input clocks data present on
TXDIN into the device.
O
LVDS
Divided Down Output Clock.
This clock output is generated by dividing down the
high speed output clock, TXCLKOUT, by a factor of 4.
It is intended for use in counter clocking schemes that
transfer data between the system ASIC and the
Si5110.
I
LVTTL
High Speed Clock Disable.
When this input is high, the output driver for TXCLK-
OUT is disabled. In applications that do not require the
output data clock, the output clock driver should be
disabled to save power.
High Speed Clock Output.
The high speed clock output, TXCLKOUT, is gener-
ated by the PLL in the clock multiplier unit. Its fre-
quency is nominally 16 times or 32 times the selected
reference source.
Preliminary Rev. 0.41
21