SI5110 Datasheet, PDF (13/26 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5110
bandwidth is controlled by a digital filter inside the
DSPLL and can be changed without any modification to
external components.
DSPLL^™ Clock Multiplier Unit
The Si5110’s clock multiplier unit (CMU) uses Silicon
Laboratories proprietary DSPLL technology to generate
a low jitter, high frequency clock source capable of
producing a high speed serial clock and data output with
significant margin to the SONET/SDH specifications.
This is achieved by using a digital signal processing
(DSP) algorithm to replace the loop filter commonly
found in analog PLL designs. This algorithm processes
the phase detector error term and generates a digital
control value to adjust the frequency of the voltage
controlled oscillator (VCO). Because external loop filter
components are not required, sensitive noise entry
points are eliminated, thus making the DSPLL less
susceptible to board-level noise sources. Therefore,
SONET/SDH jitter compliance is easier to attain in the
application.
Programmable Loop Filter Bandwidth
The digitally implemented loop filter allows for two
bandwidth settings that provide either wideband or
narrowband jitter transfer characteristics. The filter
bandwidth is selected via the BWSEL control input. In
traditional PLL implementations, changing the loop filter
bandwidth would require changing the values of
external loop filter components.
In narrowband mode, a loop filter cutoff of 6 kHz is
provided. This setting makes the Si5110 more tolerant
to jitter on the reference clock source. As a result, the
complexity of the clock distribution circuitry used to
generate the physical layer reference clocks can be
simplified without compromising jitter margin to the
SONET/SDH specification.
In wideband mode, the loop filter provides a cutoff of
25 kHz. This setting is desirable in applications where
the reference clock is provided by a low jitter source like
the Si5364 Clock Synchronization IC or Si5320
Precision Clock Multiplier/Jitter Attenuator IC. This
allows the DSPLL to more closely track the precision
reference source resulting in the best possible jitter
performance.
Serialization
The Si5110 includes serialization circuitry that combines
a FIFO with a parallel to serial shift register. Low speed
data on the parallel 4-bit input bus, TXDIN[3:0], is
latched into the FIFO on the rising edge of TXCLK4IN.
The data in the FIFO is loaded into the shift register by
TXCLK4OUT, an output clock that is produced by
dividing down the high speed transmit clock,
TXCLKOUT, by a factor of 4. The high-speed serial data
stream is clocked out of the shift register by
TXCLKOUT. The TXCLK4OUT clock output is provided
to support data word transfers between the Si5110 and
upstream devices using a counter clocking scheme.
Input FIFO
The Si5110 integrates a FIFO to decouple data
transferred into the FIFO via TXCLK4IN from data
transferred into the shift register via TXCLK4OUT. The
FIFO is eight parallel words deep and accommodates
any static phase delay that may be introduced between
TXCLK4OUT and TXCLK4IN in counter clocking
schemes. Further, the FIFO will accommodate a phase
drift or wander between TXCLK4IN and TXCLK4OUT of
up to three parallel data words.
The FIFO circuitry indicates an overflow or underflow
condition by asserting FIFOERR high. This output can
be used to recenter the FIFO read/write pointers by
tieing it directly to the FIFORST input. The Si5110 will
also recenter the read/write pointers after the device’s
power on reset, external reset via RESET, and each
time the DSPLL transitions from an out of lock state to a
locked state (TXLOL transitions from low to high).
Parallel Input To Serial Output Relationship
The Si5110 provides the capability to select the order in
which data on the parallel input bus is transmitted
serially. Data on this bus can be transmitted MSB first or
LSB first depending on the setting of TXMSBSEL. If
TXMSBSEL is tied low, TXDIN0 is transmitted first
followed in order by TXDIN1 through TXDIN3. If
TXMSBSEL is tied high, TXDIN3 is transmitted first
followed in order by TXDIN2 through TXDIN0. This
feature simplifies board routing when ICs are mounted
on both sides of the PCB.
Transmit Data Squelch
To prevent the transmission of corrupted data into the
network, the Si5110 provides a control pin that can be
used to force TXDOUT to 0. By driving TXSQLCH low,
the high speed serial output, TXDOUT will be forced to
0. Transmit data squelching is disabled when the device
is in line loopback mode (LLBK = 0).
Clock Disable
The Si5110 provides a clock disable pin, TXCLKDSBL,
that is used to disable the high-speed serial data clock
output, TXCLKOUT. When the TXCLKDSBL pin is
asserted, the positive and negative terminals of
CLKOUT are tied to 1.5 V through 50 Ω on-chip
resistors. This feature is used to reduce power
consumption in applications that do not use the high
speed transmit data clock.
Preliminary Rev. 0.41
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