SI5110 Datasheet, PDF (15/26 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5110
Transmit Differential Output Circuitry
The Si5110 utilizes a current-mode logic (CML) architecture to drive the high speed serial output clock and data on
TXCLKOUT and TXDOUT. An example of output termination with ac coupling is shown in Figure 4. In applications
where direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage
swing of the CML architecture is listed in Table 2 on page 5.
1.5 V
50 Ω
50 Ω
0.1 µF ^{Zo = 50 Ω}
VDD
50 Ω
0.1 µF Zo = 50 Ω
24 mA
50 Ω
VDD
Figure 4. CML Output Driver Termination (TXCLKOUT, TXDOUT)
Preliminary Rev. 0.41
15