SI5110 Datasheet, PDF (19/26 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5110
Pin
Number(s)
G8
Name
LPTM
C4
LTR
B5
NC
K2
NC
A2
PHASEADJ
E10, F10
REFCLK,
REFCLK
F3
REFRATE
J7
REFSEL
I/O Signal Level
Description
I
LVTTL
Loop Timed Operation.
When this input is forced high, the recovered clock
from the receiver is divided down and used as the ref-
erence source for the transmit CMU. The narrowband
setting for the DSPLL CMU will be sufficient to provide
SONET compliant jitter generation and transfer on the
transmit data and clock outputs (TXDOUT,TXCLK-
OUT). This pin should be held low for normal opera-
tion.
I
LVTTL
Lock-to-Reference.
This input forces a stable output clock by locking
RXCLK1 and RXCLK2 to the provided reference.
Driving LTR low activates this feature.
No Connect.
Reserved for device testing. Leave electrically
unconnected.
No Connect.
Reserved for device testing. Leave electrically uncon-
nected.
I
Sampling Phase Adjust.
Applying an analog voltage to this pin allows adjust-
ment of the sampling phase across the data eye. Tie-
ing this input high nominally centers the sampling
phase.
I
LVPECL ^{Differential Reference Clock.}
The reference clock sets the operating frequency of
the PLL used to generate the high speed transmit
clock. In addition, REFCLK sets the initial operating
frequency used by the onboard PLL for clock and data
recovery. The Si5110 will operate with reference clock
frequencies that are either 1/16 or 1/32 the serial data
rate (nominally 155 MHz or 78 MHz).
I
LVTTL
Reference Clock Select.
This input configures the Si5110 to operate with one of
two reference clock frequencies. If REFRATE is held
high, the device requires a reference clock that is 1/16
the serial data rate. If REFRATE is low, a reference
clock at 1/32 the serial data rate is required.
I
LVTTL
Reference Clock Selection.
This inputs selects the reference clock source used by
the CMU. When REFSEL = 0, the low speed data
input clock, TXCLK4IN, is used as the CMU refer-
ence. When REFSEL = 0, the reference clock pro-
vided on REFCLK is used.
Preliminary Rev. 0.41
19