SI5110 Datasheet, PDF (7/26 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5110
Table 3. AC Characteristics (RXDIN, RXDOUT, RXCLK1, RXCLK2)
(V_DD = 1.8 V ±5%, T_A = –40°C to 85°C)
Parameter
Output Clock Frequency
(RXCLK1)
Duty Cycle (RXCLK1, RXCLK2)
Symbol
f_clkout
Test Condition
See Figure 2
tch/tcp, Figure 2
Min
Typ
Max Unit
—
622
667 MHz
45
—
55
%
Output Rise and Fall Times
t_R,t_F
(RXCLK1, RXCLK2, RXDOUT)
Figure 3
—
50
—
ps
Data Invalid Prior to RXCLK1
t_cq1
Figure 2
—
—
200
ps
Data Invalid After RXCLK1
t_cq2
Figure 2
—
—
200
ps
Input Return Loss (RXIN)
100 kHz–2.5 GHz
2.5 GHz–4.0 GHz
18.7
—
TBD
—
—
dB
—
dB
Slicing Adjust Dynamic Range
Slicing Level Offset¹
(referred to RXDIN)
Slicing Level Accuracy
Sampling Phase Adjustment²
LOS Threshold Dynamic Range
LOS Threshold Offset³
(referred to RXDIN)
LOS Threshold Accuracy
SLICELVL = 200–800 mV –20
—
SLICELVL = 200–800 mV –500
—
VSLICE
–5
—
PHASEADJ = 200–800 mV –22.5° —
LOSLVL = 200–800 mV
10
—
LOSLVL = 200–800 mV –500
—
VLOS
–5
—
20
mV
500
µV
5
22.5°
50
500
%
mV
pk-pk
µV
5
%
Note:
1. Slice level (referred to RXDIN) is calculated as follows: VSLICE = (SLICE_LVL – 0.4 VREF)/15.
2. Sample Phase Offset is calculated as follows: PHASE OFFSET = 22.5°(PHASEADJ – 0.4 VREF)/0.3
3. LOS Threshold voltage (referred to RXDIN) is calculated as follows: VLOS = 30 mV + (LOS_LVL – 0.4 VREF)/15.
Preliminary Rev. 0.41
7