SI5110 Datasheet, PDF (14/26 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5110
Loop Timed Operation
The Si5110 can be configured to provide SONET/SDH
compliant loop timed operation. When LPTM is asserted
high, the transmit clock and data timing is derived from
the recovered clock output by the CDR. This is achieved
by dividing down the recovered clock and using it as a
reference source for the transmit CMU. This will
produce a transmit clock and data that are locked to the
timing recovered from the received data path. In this
mode, a narrow band loop filter setting is
recommended.
Diagnostic Loopback
The Si5110 supports diagnostic loopback which
establishes a loopback path from the serializer output to
the deserializer input. This provides a mechanism for
looping back data input via the low speed transmit
interface TXDIN to the low speed receive data interface
RXDOUT. This mode is enabled by forcing DLBK low.
Line Loopback
The Si5110 supports line loopback which establishes a
loopback path from the high speed receive input to the
high speed transmit output. This provides a mechanism
for looping back the high-speed clock and data
recovered from RXDIN to the transmit data output
TXDOUT and clock TXCLKOUT. This mode is enabled
by forcing LLBK low.
Bias Generation Circuitry
The Si5110 makes use of two external resistors,
RXREXT and TXREXT, to set internal bias currents for
the receive and transmit sections of the Si5110. The
external resistors allows precise generation of bias
currents that significantly reduce power consumption.
The bias generation circuitry requires 3.09 kΩ (1%)
resistors connected between RXREXT/TXREXT and
GND.
reference clock sources. The first configuration uses an
externally provided reference clock that is input via
REFCLK. The second configuration uses the parallel
data clock, TXCLK4IN, as the reference clock source.
When using TXCLK4IN as the reference source, the
narrowband loop filter setting in the CMU may be
preferable to remove jitter that may be present on the
data clock. The selection of reference clock source is
controlled via the REFSEL input.
The CMU in the Si5110’s transmit section multiplies up
the provided reference to the serial transmit data rate.
When the CMU has achieved lock with the selected
reference, the TXLOL output will be driven high.The
CDR in the receive section of the Si5110 uses a
reference clock to center the PLL frequency so that it is
close enough to the data frequency to achieve lock with
the incoming data. When the CDR has locked to the
data, RXLOL is driven high.
Reset
The Si5110 is reset by holding the RESET pin low for at
least 1 µs. When RESET is asserted low, the input FIFO
pointers reset and the digital control circuitry initializes.
When RESET transitions high to start normal operation,
the CMU will be calibrated.
Voltage Reference Output
The Si5110 provides an output voltage reference that
can be used by an external circuit to set the LOS
threshold, slicing level, or sampling phase adjustment.
One possible implementation would use a resistor
divider to set the control voltage for LOSLVL,
SLICELVL, or PHASEADJ. A second alternative would
use a DAC to set the control voltage. Using this
approach, VREF would be used to establish the range
of a DAC output. The reference voltage is nominally
1.25 V.
Reference Clock
The Si5110 is designed to operate with reference clock
sources that are either 1/16th or 1/32nd the desired
transceiver data rate. The device will support operation
with data rates between ~2.5 Gbps and ~2.7 Gbps and
the reference clock should be scaled accordingly. For
example, to support 2.67 Gbps operation the reference
clock source would be approximately 83 MHz or
167 MHz. The REFRATE input pin is used to configure
the device for operation with one of the two supported
reference clock submultiples of the data rate.
The Si5110 supports operation with two selectable
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Preliminary Rev. 0.41