SI5110 Datasheet, PDF (20/26 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5110
Pin
Number(s)
Name
I/O Signal Level
Description
E3
RESET
I
LVTTL
Device Reset.
Forcing this input low for at least 1 µs will cause a
device reset. For normal operation, this pin should be
held high.
A6, B6, C5–
6, D3, G3,
H3, J3–4
RSVD_GND
Reserved Tie To Ground.
Must tie directly to GND for proper operation.
B7–8
RXCLK1,
O
RXCLK1
LVDS
Differential Clock Output 1.
The clock recovered from the signal present on
RXDIN is divided down to the parallel output word rate
and output on RXCLK1. In the absence of data, a sta-
ble clock on RXCLK1 can be maintained by asserting
LTR.
C8
RXCLK2DIV
I
C7
RXCLK2DSBL
I
LVTTL
LVTTL
Clock Divider Select.
This input selects the divide factor used to generate
the RXCLK2 output. When this input is driven low,
RXCLK2 is equal to the output word rate on RXDOUT.
When driven high, RXCLK2 is 1/4th the output word
rate.
RXCLK2 Disable.
Driving this input high will disable the RXCLK2 output.
This would be used to save power in applications that
do not require an auxiliary clock.
A7–8
RXCLK2,
RXCLK2
B1, C1
RXDIN,
RXDIN
O
LVDS
Differential Clock Output 2.
An auxiliary output clock is provided on this pin that is
equivalent to, or a submultiple of, the output word rate.
The divide factor used in generating RXCLK2 is set
via RXCLK2DIV.
I
High Speed ^{Differential Data Input.}
Differential Clock and data are recovered from the high speed
data signal present on these pins.
A9–10, B9, RXDOUT[3:0],
O
B10, C9, RXDOUT[3:0]
C10, D9,
D10
LVDS
Differential Parallel Data Output.
The data recovered from the signal present on RXDIN
is demultiplexed and output as a 4-bit parallel word on
RXDOUT[3:0]. These outputs are updated on the ris-
ing edge of RXCLK1.
C3
RXLOL
O
LVTTL
Loss-of-Lock.
This output is driven low when the recovered clock fre-
quency deviates from the reference clock by the
amount specified in Table 5.
20
Preliminary Rev. 0.41