SI5110 Datasheet, PDF (5/26 Pages) Silicon Laboratories – SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Si5110
All
Differential
IOs
t_F
80%
20%
t_R
Figure 3. I/O Rise/Fall Times
Table 2. DC Characteristics
(V_DD = 1.8 V ±5%, T_A = –40°C to 85°C)
Parameter
Supply Current
Power Dissipation
Voltage Reference (VREF)
Common Mode Input Voltage (RXDIN)
Differential Input Voltage Swing (RXDIN)
Symbol
I_DD
P_D
V_REF
V_ICM
V_ID
Test Condition
VREF driving
10 kΩ load
See Figure 1
Min
—
—
1.21
TBD
10
Common Mode Output Voltage
(TXDOUT, TXCLKOUT)
Differential Output Voltage Swing
(TXDOUT, TXCLKOUT), Differential pk-pk
LVPECL Input Voltage HIGH (REFCLK)
LVPECL Input Voltage LOW (REFCLK)
LVPECL Input Voltage Swing,
Differential pk-pk (REFCLK)
LVPECL Internally Generated Input Bias
(REFCLK)
LVDS Input High Voltage (TXDIN,
TXCLK4IN)
LVDS Input Low Voltage (TXDIN, TXCLK4IN)
LVDS Input Voltage, Single Ended pk-pk
(TXDIN, TXCLK4IN)
LVDS Output High Voltage
(RXDOUT, RXCLK1, RXCLK2,
TXCLK4OUT)
LVDS Output Low Voltage
(RXDOUT, RXCLK1, RXCLK2,
TXCLK4OUT)
LVDS Output Voltage, Differential pk-pk
(RXDOUT, RXCLK1, RXCLK2,
TXCLK4OUT)
V_OCM
V_OD
V_IH
V_IL
V_ID
V_IB
V_IH
V_IL
V_ISE
V_OH1
V_OL1
V_OSE
.8
See Figure 1
800
Figure 1
1.975
1.32
250
1.6
—
0.0
100
100 Ω Load
Line-to-Line
100 Ω Load
Line-to-Line
100 Ω Load
Line-to-Line,
Figure 1
TBD
0.925
500
Typ
611
1.0
1.25
0.1
—
0.9
1000
2.3
1.6
—
1.95
—
—
—
—
—
—
Max
TBD
TBD
1.29
Unit
mA
W
V
TBD
1.0
1.0
V
mV
(pk-pk)
V
1200
2.59
1.99
2400
2.3
mV
(pk-pk)
V
V
mV
(pk-pk)
V
2.4
V
—
600
1.475
V
mV
(pk-pk)
mV
TBD
V
800
mV
(pk-pk)
Preliminary Rev. 0.41
5