C8051F340-GQR Datasheet, PDF (87/276 Pages) Silicon Laboratories – Full Speed USB Flash MCU Family

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
SFR Definition 9.4. PSW: Program Status Word
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Reset Value
CY
AC
F0
RS1
RS0
OV
F1
PARITY 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
(bit addressable) 0xD0
Bit7:
Bit6:
Bit5:
Bits4–3:
CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to logic 0 by all other arithmetic operations.
AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations.
F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
RS1–RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
RS1
RS0 Register Bank Address
0
0
0
0x00 - 0x07
0
1
1
0x08 - 0x0F
1
0
2
0x10 - 0x17
1
1
3
0x18 - 0x1F
Bit2:
Bit1:
Bit0:
OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY: Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
SFR Definition 9.5. ACC: Accumulator
R/W
ACC.7
Bit7
R/W
ACC.6
Bit6
R/W
ACC.5
Bit5
R/W
ACC.4
Bit4
R/W
ACC.3
Bit3
R/W
ACC.2
Bit2
R/W
R/W
Reset Value
ACC.1 ACC.0 00000000
Bit1
Bit0 SFR Address:
(bit addressable) 0xE0
Bits7–0: ACC: Accumulator.
This register is the accumulator for arithmetic operations.
Rev. 1.3
87