C8051F340-GQR Datasheet, PDF (115/276 Pages) Silicon Laboratories – Full Speed USB Flash MCU Family

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
13.2. Accessing USB FIFO Space
The C8051F34x devices include 1k of RAM which functions as USB FIFO space. Figure 13.1 shows an
expanded view of the FIFO space and user XRAM. FIFO space is normally accessed via USB FIFO regis-
ters; see Section “16.5. FIFO Management” on page 167 for more information on accessing these
FIFOs. The MOVX instruction should not be used to load or modify USB data in the FIFO space.
Unused areas of the USB FIFO space may be used as general purpose XRAM if necessary. The FIFO
block operates on the USB clock domain; thus the USB clock must be active when accessing FIFO space.
Note that the number of SYSCLK cycles required by the MOVX instruction is increased when accessing
USB FIFO space.
To access the FIFO RAM directly using MOVX instructions, the following conditions must be met: (1) the
USBFAE bit in register EMI0CF must be set to '1', and (2) the USB clock must be greater than or equal to
twice the SYSCLK (USBCLK > 2 x SYSCLK). When this bit is set, the USB FIFO space is mapped into
XRAM space at addresses 0x0400 to 0x07FF. The normal XRAM (on-chip or external) at the same
addresses cannot be accessed when the USBFAE bit is set to ‘1’.
Important Note: The USB clock must be active when accessing FIFO space.
0xFFFF
0x0800
0x07FF
0x07C0
0x07BF
0x0740
0x073F
0x0640
0x063F
On/Off-Chip XRAM
Endpoint0
(64 bytes)
Endpoint1
(128 bytes)
Endpoint2
(256 bytes)
USB FIFO Space
(USB Clock Domain)
Endpoint3
(512 bytes)
0x0440
0x043F
0x0400
0x03FF
0x0000
Free
(64 bytes)
On/Off-Chip XRAM
Figure 13.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’
Rev. 1.3
115