C8051F340-GQR Datasheet, PDF (140/276 Pages) Silicon Laboratories – Full Speed USB Flash MCU Family

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Clock Signal
USB Clock
External Oscillator
Internal Oscillator
Input Source Selection
External Oscillator / 4
Crystal Oscillator Mode
24 MHz Crystal
Register Bit Settings
USBCLK = 101b
XOSCMD = 110b
XFCN = 111b
SFR Definition 14.6. CLKSEL: Clock Select
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Reset Value
-
USBCLK
-
CLKSL
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address
0xA9
Bit 7:
Bits6–4:
Unused. Read = 0b; Write = don’t care.
USBCLK2–0: USB Clock Select
These bits select the clock supplied to USB0. When operating USB0 in full-speed mode, the
selected clock should be 48 MHz. When operating USB0 in low-speed mode, the selected
clock should be 6 MHz.
USBCLK
000
001
010
011
100
101
110
111
Selected Clock
4x Clock Multiplier
Internal Oscillator / 2
External Oscillator
External Oscillator / 2
External Oscillator / 3
External Oscillator / 4
RESERVED
RESERVED
Bit3:
Bits2–0:
Unused. Read = 0b; Write = don’t care.
CLKSL2–0: System Clock Select
These bits select the system clock source. When operating from a system clock of 25 MHz
or less, the FLRT bit should be set to ‘0’. When operating with a system clock of greater than
25 MHz (up to 48 MHz), the FLRT bit (FLSCL.4) should be set to ‘1’. See Section
“10. Prefetch Engine” on page 99 for more details.
CLKSL
Selected Clock
000
Internal Oscillator (as determined by the
IFCN bits in register OSCICN)
001
External Oscillator
010
4x Clock Multiplier / 2
011*
4x Clock Multiplier*
100
Low-Frequency Oscillator
101-111
RESERVED
*Note: This option is only available on 48 MHz devices.
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Rev. 1.3