C8051F340-GQR Datasheet, PDF (146/276 Pages) Silicon Laboratories – Full Speed USB Flash MCU Family

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
P0
P1
P2
P3
SF Signals
(32-pin
P a cka ge )
P3.1-P3.7 una va ila ble on
the 32-pin pa cka ge s
SF Signals
(48-pin
P a cka ge )
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS*
SDA
SCL
CP0
CP0A
CP1
CP1A
01234567012345670123456701234567
*NSS is only pinned out in 4-wire SPI mode
S YS CL K
CEX 0
CEX 1
CEX 2
CEX 3
CEX 4
ECI
T0
T1
T X 1**
RX1**
**UA RT1 available only on C8051F340/1/4/5/8/A /B devices
00110000100000000000000000000000
P 0S KI P [0:7]
P1S KIP[0:7]
P 2S KI P [0:7]
P 3S KI P [0:7]
Port pin assigned to peripheral by the Crossbar
SF Signa ls Special Function Signals are not assigned by the Crossbar. W hen these signals are
enabled, the Crossbar must be manually configured to skip their corresponding port pins.
Example:
XBR0 = 0x07
XBR1 = 0x43
P 0SK IP = 0x0C
P 1SK IP = 0x01
Figure 15.5. Crossbar Priority Decoder in Example Configuration (3 Pins Skipped)
Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); when either UART is selected, the Crossbar assigns both pins associated with the UART
(TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned
to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized
functions have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the
NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.
146
Rev. 1.3