C8051F340-GQR Datasheet, PDF (21/276 Pages) Silicon Laboratories – Full Speed USB Flash MCU Family

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
C2D
C2CK/RST
VDD
VREG
GND
Reset
Power-On
Reset
Supply
Monitor
Power
Net
Voltage
Regulator
Debug / Programming
Hardware
CIP-51 8051
Controller Core
64/32 kB ISP FLASH
Program Memory
256 Byte RAM
4/2 kB XRAM
XTAL1
XTAL2
System Clock Setup
External
Oscillator
Internal
Oscillator
Clock
Multiplier
Clock
Recovery
Low Freq.
Oscillator
SFR
Bus
USB Peripheral
D+
D-
VBUS
Full / Low
Speed
Transceiver
Controller
1k Byte
RAM
Port I/O Configuration
Digital Peripherals
UART0
UART1
Timers 0, 1,
2, 3
PCA/WDT
Priority
Crossbar
Decoder
SMBus
SPI
Crossbar Control
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
External Memory
Interface
P1
Control
Address
P2 / P3
P4
Data
Port 3
Drivers
Port 4
Drivers
Analog Peripherals
CP0
+
-
CP1
+
-
2 Comparators
Figure 1.3. C8051F348/C Block Diagram
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6/XTAL1
P0.7/XTAL2
P1.0
P1.1
P1.2
P1.3
P1.4/CNVSTR
P1.5/VREF
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Rev. 1.3
21