SI8250 Datasheet, PDF (8/30 Pages) Silicon Laboratories – DIGITAL POWER CONTROLLER

Si8250/1/2
Table 7. Peak Current Limit Detector Electrical Specifications
TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.
Parameter
Conditions
Min
Typ
IPK Input to DPWM Output Latency
Threshold Detector Voltage
10 mV Overdrive
VT[3:0] = 0000
—
45
35
50
VT[3:0] = 0001
VT[3:0] = 0010
85
100
135
150
VT[3:0] = 0011
185
200
VT[3:0] = 0100
VT[3:0] = 0101
235
250
285
300
VT[3:0] = 0110
335
350
VT[3:0] = 0111
VT[3:0] = 1000
485
400
435
450
VT[3:0] = 1001
VT[3:0] = 1010
VT[3:0] = 1011
485
500
535
550
585
600
VT[3:0] = 1100
VT[3:0] = 1101
635
650
685
700
Hysteresis
VT[3:0] = 1110
VT[3:0] = 1111
HYST[1:0] = 00
735
750
785
800
—
0
HYST[1:0] = 01
HYST[1:0] = 10
—
5
—
10
HYST[1:0] = 11
—
20
Blanking Time
Input Capacitance
LEB[1:0] = 00, f_PLL = 200 MHz
—
0
LEB[1:0] = 01, f_PLL = 200 MHz
—
20
LEB[1:0] = 10, f_PLL = 200 MHz
—
40
LEB[1:0] = 11, f_PLL = 200 MHz
—
80
—
4.5
Input Bias Current
Shutdown Supply Current
Enable bit = 0
—
0.1
—
0.1
Active Supply Current
IIN = (Vt + 100 mVpp),
1.5 MHz sq. wave
—
100
Max Units
—
ns
65
mV
115
165
215
265
315
365
415
465
515
565
615
665
715
765
815
—
mV
—
—
—
—
ns
—
—
—
—
pF
—
µA
—
µA
—
µA
8
Preliminary Rev. 0.8