SI8250 Datasheet, PDF (24/30 Pages) Silicon Laboratories – DIGITAL POWER CONTROLLER

Si8250/1/2
Name
P0.7
P0.6
P0.5
P0.4
P0.3/XCLK
P0.2
P0.1
P0.0
PH6
PH5
PH4
VDD
GND
PH3
PH2
PH1
Table 17. Pin Descriptions (Continued)
QFN-28
Pin #
15
16
17
18
19
20
21
22
23
24
25
—
—
26
27
28
LQFP-32
Pin#
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Type
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
DOUT
DOUT
DOUT
AIN
AIN
DOUT
DOUT
DOUT
Description
Port 0 I/O
Port 0 I/O
Port 0 I/O
Port 0 I/O
Port 0 I/O
Port 0 I/O
Port 0 I/O
Port 0 I/O or bidirectional debug data
Phase 6 switch control output
Phase 5 switch control output
Phase 4 switch control output
Power supply input
Ground
Phase 3 switch control output
Phase 2 switch control output
Phase 1 switch control output
Pin Functions:
RST/C2CK: CPU reset or debug tool clock. Driving this pin low resets the CPU. This pin is also clocked by the USB
debug adaptor during debug.
IPK: Input to the peak current detector for pulse-by-pulse current limiting and over-current protection shutdown
control.
VSENSE: ADC1 inverting input. This is the voltage feedback input for the Si8250. The maximum allowable signal is
VREF.
GND: Digital ground for the 32LQFP package, and the main ground for the 28MLP package.
GNDA: Analog ground for 32LQFP only.
VDD: Digital supply voltage for the 32LQFP package, and main supply voltage for the 28MLP package.
VDDA: Analog supply for 32LQFP only.
P1.0/VIN or AIN0: Programmable multifunction I/O pin. This pin can be software configured to be either a Port 1
digital input or output, or an ADC0 input at AMUX address 0. If used in a non-isolated application, positive input
supply voltage must be tied to this input through a resistor divider and anti-aliasing capacitor to minimize the
frequencies above fS/2 (100Khz) to prevent aliasing. Isolated applications may use this input as general-purpose
digital I/O or analog input.
P1.1 or AIN1–P1.7 or AIN7: Programmable multifunction I/O pins. These pins can be software configured to be a
Port 1 digital input or output, or an ADC0 input. P1.7 also serves as the debug data input (C2D) and is used during
debug by the USB debug adaptor. P1.7 may be used as general-purpose digital I/O when not in debug mode. Any
of the digital peripherals may be programmed to connect to these pins.
P0.0–P0.7: Programmable multifunction I/O pins. These pins can be software configured to be either a Port 1
digital input or output, or an ADC0 input. Any of the digital peripherals (including the ENABLE input) may be
programmed to connect to these pins. P0.3 may be programmed to serve as an external (25MHz nominal) clock
input.
PH1–PH6: DPWM gate control (complementary drive) outputs. These signals connect to the MOSFET gates
through an external gate driver. The output levels swing between ground and Vdd.
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Preliminary Rev. 0.8