SI8250 Datasheet, PDF (22/30 Pages) Silicon Laboratories – DIGITAL POWER CONTROLLER

Si8250/1/2
In both cases, the bias supplies must be filtered using low ESR/ESL capacitors placed close to the IC pins.
Thick copper traces should be connected to the bias pins (VDD, VDDA) and the ground pins (GND, GNDA) to
reduce resistance and inductance. The copper routings from the drivers to the FETs should be kept short and wide,
especially in very high frequency applications, to reduce inductance of the traces so that the drive signals can be
kept clean.
Connections between VSENSE and the output voltage must be kept absolutely as short as possible to minimize
inductance and parasitic ringing effects. It is best to locate the Si8250/1/2 as close to the output voltage terminal as
possible and use a Kelvin connection to ensure to difference in ground potential between the Si8250/1/2 and the
output voltage ground return.
Most applications will require access to the debug pins. These pins are susceptible to damage from electrostatic
discharge (ESD). It is therefore recommended the debug circuit interface use the input protection circuitry shown in
Figure 11.
Si8250/1/2
10
10
Debug Pins
(C2D, C2CK)
DEBUG
CONNECTOR
Figure 11. Debug Interface Pin Protection Circuit
22
Preliminary Rev. 0.8