SI8250 Datasheet, PDF (16/30 Pages) Silicon Laboratories – DIGITAL POWER CONTROLLER

Si8250/1/2
3.1. System Operation
Figure 2 shows the Si8250/1/2 controlling a non-
isolated DC/DC converter operating in digital voltage
mode control. The output voltage signal connects to the
VSENSE input through a resistive divider, limiting the
common mode voltage range applied to ADC1 to a
maximum of VREF. The equivalent resistance of the
divider and the capacitor form an anti-aliasing filter with
a cutoff frequency equal to ADC1 sampling frequency of
divided by 2 (the amplitudes of frequencies above fS/2
must be minimized to prevent aliasing).
Differential ADC1 and the DSP Filter Engine together
perform the same function as an analog error amplifier
and associated RC compensation network. ADC1
digitizes the difference between the scaled output
voltage and a programmable reference voltage provided
by the REFDAC. The ADC1 output signal is frequency
compensated (in digital domain) by the DSP Filter
Engine. The resulting output from the DSP Filter Engine
is a digital code that represents the compensated duty
cycle ratio, u(n). The digital PWM generator (DPWM)
directly varies output timing to the external gate drivers
based on the value of u(n) until the difference between
VSENSE and ADC1 reference level is driven to zero.
Sensing circuitry within the power stages (current
transformer, sense amp, etc.) provides a signal
representative of inductor or transformer current. This
signal connects to the pulse-by-pulse current limiting
hardware in the Si8250/1/2 via the IPK input pin. This
current limiting circuitry is similar to that found in a
voltage mode analog PWM. It contains a fast analog
comparator and a programmable leading-edge blanking
circuit to prevent unwanted tripping of the current
sensing circuitry on the leading edge of the current
pulse. Current limiting occurs when the sensed current
exceeds the programmed threshold. When this occurs,
the on-going active portions of the PWM outputs are
terminated. A programmable OCP counter keeps track
of the number of consecutive current limit cycles, and
automatically shuts the supply down when the
accumulated number of limit cycles exceeds the
programmed maximum.
The System Management Processor is based on a 50
million instruction per second (MIPS) 8051 CPU and
dedicated A/D converter (ADC0). ADC0 digitizes key
analog parameters that are used by the MCU to provide
protection, as well as manage and control other aspects
of the power system. On-board digital peripherals
include: timers, an SMBus interface port (for PMBus or
other protocols); and a universal asynchronous
receiver/transmitter (UART) for serial communications,
useful for communicating across an isolation boundary.
The System Management Processor serves several
purposes, among these are:
1. Continuously optimizes Control Processor operation
(e.g. efficiently optimization)
2. Executes user-specific algorithms (e.g. support for
proprietary system interfaces)
3. Provides regulation for low-bandwidth system
variables (e.g. VIN feed-forward)
4. Performs system fault detection and recovery
5. Provides system housekeeping functions such as
PMBus communication support
6. Manages external device functions (e.g. external
supply sequencing, fan control/monitoring)
The Si8250/1/2 system development requires using the
Si8250DK, a comprehensive development kit providing
all required hardware and software for control system
design. It comes complete with pre-written and verified
application software, and a set of tools that enable the
user to adapt this software to the end application. It also
includes a turnkey isolated half-bridge DC/DC converter
based on the Si8250/1/2 for evaluation and
experimentation.
3.2. Control Processor Functional Block
Descriptions (Figure 1)
ADC 1: Differential input, 10 Msps control loop analog-
to-digital converter. ADC1 digitizes the difference
between the Vsense input and the programmable
voltage reference level from the REFDAC. ADC1 can be
operated at either 5 Msps or 10 Msps and has a
programmable LSB size to prevent limit cycle oscillation
(Limit cycle oscillation can also be avoided using
dithering to increase DPWM resolution). ADC1 has
programmable conversion rates of 10 Msps and 5 Msps
to accommodate a wide loop gain range. ADC1 also
contains a hardware transient detector that interrupts
the CPU at the onset of an output load or unload
transient. The CPU responds by executing specific
algorithms to accelerate output recovery. These
algorithms may include increasing loop bandwidth or
other measures.
REFDAC: 9-bit digital-to-analog converter provides the
output voltage reference setting. The REFDAC uses the
on-board band gap as its voltage reference, or can be
referenced to an external voltage reference source.
REFDAC is used for output voltage calibration,
margining and positioning. The CPU continuously
manages the REFDAC during soft-start and soft-stop.
DSP Filter Engine: This two-stage loop compensation
filter is the functional equivalent of an active RC
compensation in an analog control scheme. The first
filter stage is a PID filter providing one pole and two
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Preliminary Rev. 0.8