SI8250 Datasheet, PDF (11/30 Pages) Silicon Laboratories – DIGITAL POWER CONTROLLER

Si8250/1/2
Table 11. Reset Electrical Characteristics
TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Pull-up Current
I_OL = 8.5mA, VDD = 2.5V
—
—
0.7
0.7 x V_DD
—
—
—
—
0.3 x V_DD
RST = 0.0
—
25
TBD
VDD POR Threshold
2.0
2.1
2.2
Missing clock detector timeout Time from last system clock ris-
—
ing edge to start of reset
250
650
Reset time delay
Delay between release of any
5.0
—
—
reset source and code execu-
tion at location 0x0000
Minimum RST Low time to gen-
erate a System Reset
6.5
—
—
VDD monitor turn-on time
100
—
—
VDD monitor supply current
—
40
—
Units
V
V
V
µA
V
µs
µs
µs
µs
µA
Table 12. Flash Electrical Characteristics
TA = –40 to +125 °C, VDD = 2.25 V – 2.75 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.
Parameter
Flash Size
Conditions
Si8250
Si8251, Si8252
Min
Typ
32768⁽¹⁾
—
16383⁽¹⁾
—
Max
—
—
Units
bytes
Endurance
Read Cycle Time
10 K 100 K
—
Erase/Write
TBD
—
—
ns
Erase Cycle Time
50 MHz System Clock
32
—
48
ms
Write Cycle Time
50 MHz System Clock
76
—
114
µs
Notes:
1. The last 512 bytes of memory are reserved.
Preliminary Rev. 0.8
11