SI8250 Datasheet, PDF (15/30 Pages) Silicon Laboratories – DIGITAL POWER CONTROLLER

3. Product Description
Si8250/1/2
VDD
SYSCLKIN
DEBUG
PORT
System Management Processor
2% 25 Mhz OSC,
and LFO
RESET
CONTROL
HARDWARE
DEBUG
16/32 kB
Flash
1280 Byte
RAM
4x 16-BIT
TIMERS
SMBus
3 CH PCA
I/O PORT
LATCHES
UART
INTERRUPT
CONTROL
ADC
REGISTERS
& LIMIT
DETECTORS
VSENSE
12-BIT
200 Ksps
8
ADC
AUTO
SCAN
LOGIC
TEMP
SENSOR
I/O (8)
I/O (8)
VSENSE
VREF
IPK
VSENSE
VREF
REFDAC
10 MHz
ADC
DSP
FILTER ENGINE
Pulse-by-Pulse
Current Limiter
and OCP
Control Processor
ICYC
OCP
u(n)
MULTIPHASE GATE CONTROL
DPWM
(6)
Si8250/1/2
Figure 1. Functional Block Diagram
VDD
SYSCLKIN
DEBUG
PORT
System Management Processor
50MIPS 8051 CPU
and Memory
Digital Peripherals:
- UART
- SMBus Port
- 4 x 16-Bit Timers
- 3 Ch PCA (PWM)
- I/O Port Latches
16 General-Purpose
Analog/Digital I/O Lines
ADC 0
12-Bit, 200Ksps
10-Channel
VSENSE
TEMP
SENSOR
Analog Input (e.g. average current)
Digital Ouput (e.g. fan speed control)
VSENSE
VREF
IPK
VSENSE
VREF REFDAC
ADC1
10Msps
DSP
FILTER ENGINE
Pulse-by-Pulse
Current Limiter
and OCP
Control Processor
ICYC
OCP
u(n)
MULTIPHASE
DPWM
SUPPLY INPUT
VOLTAGE
Up to 6 Gate
Control Outputs
Si8250
GATE
DRIVERS
POWER STAGES
SWITCHES
AND
MAGNETICS
OUTPUT
FILTER
VOUT
Peak Current Signal (e.g. CT)
Figure 2. Si8250 Top-Level Block Diagram
Preliminary Rev. 0.8
15