SI8250 Datasheet, PDF (6/30 Pages) Silicon Laboratories – DIGITAL POWER CONTROLLER

Si8250/1/2
Table 4. ADC0 (12-Bit ADC) Specifications
TA = –40 to +125 °C, VDD = 2.5 V, SYSCLK = 25 MHz, PLLCLK = 200 MHz unless otherwise specified.
Parameter
Conditions
Min Typ Max
Units
DC Accuracy
Resolution
—
12
—
bits
Integral Nonlinearity
Differential Nonlinearity
Guaranteed Monotonic
—
—
±2
LSB
—
—
±1
LSB
Offset Error
—
±3
—
LSB
Full Scale Error
Offset Temperature Coefficient
Differential mode
—
3
—
— TBD —
LSB
ppm/°C
Dynamic Performance (10 kHz sine-wave Single-ended input, 0 to 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
—
64
—
dB
Up to the 5^th harmonic
—
83
—
dB
Spurious-Free Dynamic Range
Conversion Rate
Conversion Time in SAR Clocks
Note 1
— –73 —
—
13
—
dB
clocks
Track/Hold Acquisition Time
Throughput Rate
Note 2
1
—
—
—
—
200
µs
ksps
Analog Inputs
Input Voltage Range
Input Capacitance
0
—
V_REF
V
—
15
—
pF
Temperature Sensor
Linearity
Notes 3, 4
— ±TBD —
°C
Gain
Notes 3, 4
— 1353 —
µV/°C
Offset
Power Specifications
Notes 3, 4 (Temp = 0 °C)
—
488
—
mV
Power Supply Current (V_DD sup-
plied to ADC0)
Operating Mode, 200 ksps
—
780
—
Power-On Time
After V_REF settle, before tracking —
5
—
begins
Power Supply Rejection
— TBD —
µA
µs
mV/V
Notes:
1. An additional 2 F_CLK cycles are required to start and complete a conversion.
2. Additional tracking time may be required depending on the output impedance connected to the ADC input.
3. Represents one standard deviation from the mean.
4. Includes ADC offset, gain, and linearity variations.
6
Preliminary Rev. 0.8