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SI5376 Datasheet, PDF (8/66 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR | |||
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Si5376
Table 3. AC Characteristics
(VDD = 1.8 ± 5%, 2.5 ±10%, TA = â40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Single-Ended Reference Clock Input Pin OSC_P (OSC_N with cap to GND)1
OSC_P to OSC_N
OSCRIN
RATE_REG = 0101 or
â
100
Resistance
0110, ac coupled
Input Voltage Swing
OSCVPP
RATE_REG = 0101 or
0.5
â
0110, ac coupled
Differential Reference Clock Input Pins (OSC_P/OSC_N)1
Input Voltage Swing
OSCVPP
RATE_REG = 0101 or
0.5
â
0110, ac coupled
CKINn Input Pins
Input Frequency
Input Duty Cycle
(Minimum Pulse
Width)
CKNF
0.002
â
CKNDC
Whichever is smaller
40
â
(i.e., the 40% / 60%
limitation applies only
to high-frequency
clocks)
2
â
Input Rise/Fall Time
CKNTRF
20â80%
See Figure 2
â
â
CKOUTn Output Pins
Output Frequency
(Output not config-
ured for CMOS or
Disabled)
CKOF
0.002
â
Maximum Output
Frequency in CMOS
Format
CKOF
â
â
Output Rise/Fall
(20â80 %) @
CKOTRF Output not configured for
â
230
CMOS or Disabled
622.08 MHz output
See Figure 2
Output Rise/Fall
(20â80%) @
212.5 MHz output
Output Rise/Fall
(20â80%) @
212.5 MHz output
CKOTRF
CKOTRF
CMOS Output
VDD = 1.71
CLOAD = 5 pF
CMOS Output
VDD = 2.25
CLOAD = 5 pF
â
â
â
â
Notes:
1. A crystal may not be used in place of an oscillator.
2. Input to output skew after an ICAL is not controlled and can be any value.
Max
â
1.2
2.4
710
60
â
11
808
212.5
350
8
2
Unit
ï
VPP
VPP
MHz
%
ns
ns
MHz
MHz
ps
ns
ns
8
Rev. 1.0
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