SI5376 Datasheet, PDF (15/66 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5376
4. Functional Description
CKIN1P_A
CKIN1N_A
CKIN2P_A
CKIN2N_A
Internal
Osc
CKIN3P_B
CKIN3N_B
CKIN4P_B
CKIN4N_B
Internal
Osc
CKIN5P_C
CKIN5N_C
CKIN6P_C
CKIN6N_C
Internal
Osc
CKIN7P_D
CKIN7N_D
CKIN8P_D
CKIN8N_D
Internal
Osc
Input Stage PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
Hitless
Switch
PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
Hitless
Switch
PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
Hitless
Switch
PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
Hitless
Switch
Synthesis Stage
DSPLL^®
A
fOSC
÷ NC1_HS
÷ N2
DSPLL^®
B
fOSC
÷ NC1_HS
÷ N2
DSPLL^®
C
fOSC
÷ NC1_HS
÷ N2
DSPLL^®
D
fOSC
÷ NC1_HS
÷ N2
RSTL_q
CS_CA_q
Status / Control
SCL SDA LOL_q IRQ_q
OSC_P/N
Low Jitter
XO or Clock
Output Stage
PLL Bypass
÷ NC1
÷ NC2
PLL Bypass
PLL Bypass
÷ NC1
÷ NC2
PLL Bypass
PLL Bypass
÷ NC1
÷ NC2
PLL Bypass
PLL Bypass
÷ NC1
÷ NC2
PLL Bypass
High PSRR
Voltage Regulator
CKOUT1P_A
CKOUT1N_A
CKOUT2P_A
CKOUT2N_A
CKOUT3P_B
CKOUT3N_B
CKOUT4P_B
CKOUT4N_B
CKOUT5P_C
CKOUT5N_C
CKOUT6P_C
CKOUT6N_C
CKOUT7P_D
CKOUT7N_D
CKOUT8P_D
CKOUT8N_D
VDD_q
GND
Figure 4. Functional Block Diagram
The Si5376 is a highly integrated jitter-attenuating clock multiplier that integrates four fully independent DSPLLs
and provides ultra-low jitter generation with less than 410 fs RMS. Configuration and control of the Si5376 is mainly
handled through the I²C interface. The device accepts clock inputs ranging from 2 kHz to 710 MHz and generates
independent, synchronous clock outputs ranging from 2 kHz to 808 MHz for each DSPLL. Virtually any frequency
translation (M/N) combination across its operating range is supported. The Si5376 supports a digitally
programmable loop bandwidth that can range from 60 Hz to 8.4 kHz requiring no external loop filter components.
An external single-ended or differential reference clock or XO is required for the device to enable ultra-low jitter
generation and jitter attenuation.
The device monitors each input clock for loss-of-signal (LOS) and provides a LOS alarm when missing pulses on
any of the input clocks are detected. The device monitors the lock status of each DSPLL and provides a Loss-of-
Lock (LOL) alarm when the DSPLL is unlocked. The lock detect algorithm continuously monitors the phase of the
selected input clock in relation to the phase of the feedback clock. The Si5376 provides a holdover capability that
allows the device to continue generation of a stable output clock when the input reference is lost. The reference
oscillator can be internally routed into CKIN2_q, so free-running clock generation is supported for each DSPLL
offering simultaneous synchronous and asynchronous operation.
The output drivers are configurable to support common signal formats, such as LVPECL, LVDS, CML, and CMOS
loads. If the CMOS signal format is selected, each differential output buffer generates two in-phase CMOS clocks
at the same frequency. For system-level debugging, a DSPLL bypass mode drives the clock output directly from
the selected input clock, bypassing the internal DSPLL.
Silicon Laboratories offers a PC-based software utility, Si537xDSPLLsim that can be used to determine valid
frequency plans and loop bandwidth settings to simplify device setup. Si537xDSPLLsim provides the optimum
input, output, and feedback divider values for a given input frequency and clock multiplication ratio that minimizes
phase noise. This utility can be downloaded from http://www.silabs.com/timing. For further assistance, refer to the
Si53xx Any-Frequency Precision Clocks Family Reference Manual.
Rev. 1.0
15