SI5376 Datasheet, PDF (60/66 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5376
Pin #
B1
A2
A5
A4
A9
B9
E9
D9
Table 10. Si5376 Pin Descriptions (Continued)
Pin Name I/O
CKOUT1P_A O
CKOUT1N_A
CKOUT2P_A
CKOUT2N_A
CKOUT1P_B
CKOUT1N_B
CKOUT2P_B
CKOUT2N_B
Signal
Level
Multi
Description
Output Clock for DSPLLq.
Differential output clocks. Output signal format is selected by
SFOUT_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both out-
put pins drive in phase single-ended clock outputs at the same
frequency.
J9
CKOUT1P_C
J8
CKOUT1N_C
J5
CKOUT2P_C
J6
CKOUT2N_C
J1
CKOUT1P_D
H1
CKOUT1N_D
E1
CKOUT2P_D
F1
CKOUT2N_D
Note: Internal register names are indicated by italics, e.g., IRQ_PIN. See Si5376 Register Map.
60
Rev. 1.0