SI5376 Datasheet, PDF (26/66 Pages) Silicon Laboratories – 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5376
Register 6.
Bit
D7
D6
Name
Type
R
R
Reset value = 0010 1101
D5
D4
D3
SFOUT2_REG [2:0]
R/W
D2
D1
D0
SFOUT1_REG [2:0]
R/W
Bit
Name
Function
7:6
Reserved
5:3 SFOUT2_ SFOUT2_REG [2:0].
REG [2:0] _{Controls output signal format and disable for CKOUT2 output buffer.}
000: Reserved
001: Disable CKOUT2
010: CMOS (Bypass mode not supported)
011: Low swing LVDS
100: Reserved
101: LVPECL (not available when V_DD = 1.8 V)
110: CML
111: LVDS
2:0 SFOUT1_ SFOUT1_REG [2:0].
REG [2:0] _{Controls output signal format and disable for CKOUT1 output buffer.}
000: Reserved
001: Disable CKOUT1
010: CMOS (Bypass mode not supported)
011: Low swing LVDS
100: Reserved
101: LVPECL (not available when V_DD = 1.8 V)
110: CML
111: LVDS
26
Rev. 1.0